kernel.git/arch/powerpc/kernel/cpu_setup_fsl_booke.S, branch linux-3.8.y

powerpc/booke: Add CPU_FTR_EMB_HV check for e5500.

2012-09-12T19:57:09Z

Added CPU_FTR_EMB_HV feature check for e5500. Signed-off-by: Varun Sethi Signed-off-by: Mihai Caraman Signed-off-by: Kumar Gala

powerpc/booke: Separate out restore_e5500/setup_e5500 routines.

2012-09-12T19:57:09Z

For the 64 bit case separate out e5500 cpu_setup and cpu_restore functions. The cpu_setup function (for the primary core) is passed the cpu_spec pointer, which is not there in case of the cpu_restore function. Also, in our case we will have to manipulate the CPU_FTR_EMB_HV flag on the primary core. Signed-off-by: Varun Sethi Signed-off-by: Kumar Gala

powerpc/booke: Merge the 32 bit e5500/e500mc cpu setup code.

2012-09-12T19:57:09Z

Merge the 32 bit cpu setup code for e500mc/e5500 and define the "cpu_restore" routine (for e5500/e6500) only for the 64 bit case. The cpu_restore routine is used in the 64 bit case for setting up the secondary cores. Signed-off-by: Varun Sethi Signed-off-by: Kumar Gala

powepc/booke: Separate out E.HV check and ivor setup code.

2012-09-12T19:57:08Z

Move the E.HV check and CPU_FTR_EMB_HV flag manipulation to the cpu setup code. Create a separate routine for E.HV ivors setup. Signed-off-by: Varun Sethi Signed-off-by: Kumar Gala

KVM: PPC: e500mc support

2012-04-08T09:54:33Z

Add processor support for e500mc, using hardware virtualization support (GS-mode). Current issues include: - No support for external proxy (coreint) interrupt mode in the guest. Includes work by Ashish Kalra , Varun Sethi , and Liu Yu . Signed-off-by: Scott Wood Signed-off-by: Alexander Graf Signed-off-by: Avi Kivity

powerpc/e5500: set non-base IVORs

2011-05-19T05:36:43Z

Without this, we attempt to use doorbells for IPIs, and end up branching to some bad address. Plus, even for the exceptions we don't implement, it's good to handle it and get a message out. Signed-off-by: Scott Wood Signed-off-by: Kumar Gala

rapidio: modify configuration to support PCI-SRIO controller

2011-03-24T02:46:42Z

1. Add an option to include RapidIO support if the PCI is available. 2. Add FSL_RIO configuration option to enable controller selection. 3. Add RapidIO support option into x86 and MIPS architectures. Signed-off-by: Alexandre Bounine Acked-by: Kumar Gala Cc: Matt Porter Cc: Li Yang Cc: Thomas Moll Cc: Micha Nelissen Cc: Benjamin Herrenschmidt Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

powerpc/fsl_rio: Fix non-standard HID1 register access

2011-01-13T00:00:29Z

Moved setting of RFXE bit so we get machine checks on RIO errors into cpu_setup so that the RIO code isn't core specific. Signed-off-by: Shaohui Xie Cc: Li Yang Cc: Roy Zang Cc: Alexandre Bounine Signed-off-by: Kumar Gala

powerpc/fsl-booke: Add support for FSL 64-bit e5500 core

2010-10-14T05:55:03Z

The new e5500 core is similar to the e500mc core but adds 64-bit support. We support running it in 32-bit mode as it is identical to the e500mc. Signed-off-by: Kumar Gala

powerpc/fsl-booke: Enable L1 cache on e500v1/e500v2/e500mc CPUs

2009-06-16T02:45:30Z

Some boot loaders may not enable L1 instruction/data cache. Check if data and instruction caches are enabled, and enable them if needed. Signed-off-by: Nate Case Signed-off-by: Kumar Gala