kernel.git/arch/powerpc/include/asm/system.h, branch linux-2.6.34.y

powerpc/booke: Add support for advanced debug registers

2010-02-17T03:03:17Z

powerpc/booke: Add support for advanced debug registers From: Dave Kleikamp Based on patches originally written by Torez Smith. This patch defines context switch and trap related functionality for BookE specific Debug Registers. It adds support to ptrace() for setting and getting BookE related Debug Registers Signed-off-by: Dave Kleikamp Cc: Torez Smith Cc: Benjamin Herrenschmidt Cc: David Gibson Cc: Josh Boyer Cc: Kumar Gala Cc: Sergio Durigan Junior Cc: Thiago Jung Bauermann Cc: linuxppc-dev list Signed-off-by: Benjamin Herrenschmidt

powerpc: Rename LWSYNC_ON_SMP to PPC_RELEASE_BARRIER, ISYNC_ON_SMP to PPC_ACQUIRE_BARRIER

2010-02-17T03:03:15Z

For performance reasons we are about to change ISYNC_ON_SMP to sometimes be lwsync. Now that the macro name doesn't make sense, change it and LWSYNC_ON_SMP to better explain what the barriers are doing. Signed-off-by: Anton Blanchard Signed-off-by: Benjamin Herrenschmidt

powerpc: Set init_bootmem_done on NUMA platforms as well

2009-06-09T06:43:04Z

For some obscure reason, we only set init_bootmem_done after initializing bootmem when NUMA isn't enabled. We even document this next to the declaration of that global in system.h which of course I didn't read before I had to debug why some WIP code wasn't working properly... This patch changes it so that we always set it after bootmem is initialized which should have always been the case... go figure ! Signed-off-by: Benjamin Herrenschmidt

powerpc: Allow mem=x cmdline to work with 4G+

2009-05-15T06:43:41Z

We're currently choking on mem=4g (and above) due to memory_limit being specified as an unsigned long. Make memory_limit phys_addr_t to fix this. Signed-off-by: Becky Bruce Signed-off-by: Benjamin Herrenschmidt

powerpc: Randomise lower bits of stack address

2009-02-23T04:53:20Z

Randomise the lower bits of the stack address. More randomisation is good for security but the scatter can also help with SMT threads that share an L1. A quick test case shows this working: int main() { int sp; printf("%x\n", (unsigned long)&sp & 4095); } before: 80 80 80 80 80 after: 610 490 300 6b0 d80 Signed-off-by: Anton Blanchard Signed-off-by: Benjamin Herrenschmidt

powerpc: Optimise smp_rmb

2008-11-19T05:04:57Z

After commit 598056d5af8fef1dbe8f96f5c2b641a528184e5a ("[POWERPC] Fix rmb to order cacheable vs. noncacheable"), rmb() becomes a sync instruction, which is needed to order cacheable vs noncacheable loads. However smp_rmb() is #defined to rmb(), and smp_rmb() can be an lwsync. This restores smp_rmb() performance by using lwsync there and updates the comments. Signed-off-by: Nick Piggin Signed-off-by: Paul Mackerras

powerpc: Optimise smp_wmb

2008-11-19T05:04:55Z

Change 2d1b2027626d5151fff8ef7c06ca8e7876a1a510 ("powerpc: Fixup lwsync at runtime") removed __SUBARCH_HAS_LWSYNC, causing smp_wmb to revert back to eieio for all CPUs. This restores the behaviour intorduced in 74f0609526afddd88bef40b651da24f3167b10b2 ("powerpc: Optimise smp_wmb on 64-bit processors"). Signed-off-by: Nick Piggin Signed-off-by: Paul Mackerras

powerpc: Move include files to arch/powerpc/include/asm

2008-08-04T02:02:00Z

from include/asm-powerpc. This is the result of a mkdir arch/powerpc/include/asm git mv include/asm-powerpc/* arch/powerpc/include/asm Followed by a few documentation/comment fixups and a couple of places where was being used explicitly. Of the latter only one was outside the arch code and it is a driver only built for powerpc. Signed-off-by: Stephen Rothwell Signed-off-by: Paul Mackerras