<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/arch/powerpc/include/asm/switch_to.h, branch linux-4.10.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-4.10.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-4.10.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2016-08-10T06:34:20Z</updated>
<entry>
<title>powerpc/ptrace: Fix coredump since ptrace TM changes</title>
<updated>2016-08-10T06:34:20Z</updated>
<author>
<name>Cyril Bur</name>
</author>
<published>2016-08-10T05:44:46Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=c7a318ba868c61fc9be710a4970172d8c2eeb8b9'/>
<id>urn:sha1:c7a318ba868c61fc9be710a4970172d8c2eeb8b9</id>
<content type='text'>
Commit 8d460f6156cd ("powerpc/process: Add the function
flush_tmregs_to_thread") added flush_tmregs_to_thread() and included
the assumption that it would only be called for a task which is not
current.

Although this is correct for ptrace, when generating a core dump, some
of the routines which call flush_tmregs_to_thread() are called. This
leads to a WARNing such as:

  Not expecting ptrace on self: TM regs may be incorrect
  ------------[ cut here ]------------
  WARNING: CPU: 123 PID: 7727 at arch/powerpc/kernel/process.c:1088 flush_tmregs_to_thread+0x78/0x80
  CPU: 123 PID: 7727 Comm: libvirtd Not tainted 4.8.0-rc1-gcc6x-g61e8a0d #1
  task: c000000fe631b600 task.stack: c000000fe63b0000
  NIP: c00000000001a1a8 LR: c00000000001a1a4 CTR: c000000000717780
  REGS: c000000fe63b3420 TRAP: 0700   Not tainted  (4.8.0-rc1-gcc6x-g61e8a0d)
  MSR: 900000010282b033 &lt;SF,HV,VEC,VSX,EE,FP,ME,IR,DR,RI,LE,TM[E]&gt;  CR: 28004222  XER: 20000000
  ...
  NIP [c00000000001a1a8] flush_tmregs_to_thread+0x78/0x80
  LR [c00000000001a1a4] flush_tmregs_to_thread+0x74/0x80
  Call Trace:
   flush_tmregs_to_thread+0x74/0x80 (unreliable)
   vsr_get+0x64/0x1a0
   elf_core_dump+0x604/0x1430
   do_coredump+0x5fc/0x1200
   get_signal+0x398/0x740
   do_signal+0x54/0x2b0
   do_notify_resume+0x98/0xb0
   ret_from_except_lite+0x70/0x74

So fix flush_tmregs_to_thread() to detect the case where it is called on
current, and a transaction is active, and in that case flush the TM regs
to the thread_struct.

This patch also moves flush_tmregs_to_thread() into ptrace.c as it is
only called from that file.

Fixes: 8d460f6156cd ("powerpc/process: Add the function flush_tmregs_to_thread")
Signed-off-by: Cyril Bur &lt;cyrilbur@gmail.com&gt;
[mpe: Flesh out change log]
Signed-off-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
</content>
</entry>
<entry>
<title>powerpc/process: Add the function flush_tmregs_to_thread</title>
<updated>2016-08-01T01:15:15Z</updated>
<author>
<name>Anshuman Khandual</name>
</author>
<published>2016-07-28T02:57:31Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=8d460f6156cd55d981d109f01b82cbea8cf80e57'/>
<id>urn:sha1:8d460f6156cd55d981d109f01b82cbea8cf80e57</id>
<content type='text'>
This patch creates a function flush_tmregs_to_thread which
will then be used by subsequent patches in this series. The
function checks for self tracing ptrace interface attempts
while in the TM context and logs appropriate warning message.

Signed-off-by: Anshuman Khandual &lt;khandual@linux.vnet.ibm.com&gt;
Signed-off-by: Simon Guo &lt;wei.guo.simon@gmail.com&gt;
Signed-off-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
</content>
</entry>
<entry>
<title>powerpc: Add the ability to save VSX without giving it up</title>
<updated>2016-03-02T12:34:50Z</updated>
<author>
<name>Cyril Bur</name>
</author>
<published>2016-02-29T06:53:51Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=bf6a4d5b75d1ea87897fe68d0e45d35a2996c678'/>
<id>urn:sha1:bf6a4d5b75d1ea87897fe68d0e45d35a2996c678</id>
<content type='text'>
This patch adds the ability to be able to save the VSX registers to the
thread struct without giving up (disabling the facility) next time the
process returns to userspace.

This patch builds on a previous optimisation for the FPU and VEC registers
in the thread copy path to avoid a possibly pointless reload of VSX state.

Signed-off-by: Cyril Bur &lt;cyrilbur@gmail.com&gt;
Signed-off-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
</content>
</entry>
<entry>
<title>powerpc: Add the ability to save Altivec without giving it up</title>
<updated>2016-03-02T12:34:49Z</updated>
<author>
<name>Cyril Bur</name>
</author>
<published>2016-02-29T06:53:50Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=6f515d842e8e1b205e54f44b9013bf14870b97a7'/>
<id>urn:sha1:6f515d842e8e1b205e54f44b9013bf14870b97a7</id>
<content type='text'>
This patch adds the ability to be able to save the VEC registers to the
thread struct without giving up (disabling the facility) next time the
process returns to userspace.

This patch builds on a previous optimisation for the FPU registers in the
thread copy path to avoid a possibly pointless reload of VEC state.

Signed-off-by: Cyril Bur &lt;cyrilbur@gmail.com&gt;
Signed-off-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
</content>
</entry>
<entry>
<title>powerpc: Add the ability to save FPU without giving it up</title>
<updated>2016-03-02T12:34:49Z</updated>
<author>
<name>Cyril Bur</name>
</author>
<published>2016-02-29T06:53:49Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=8792468da5e12e77e76e1edf081acf0392abb331'/>
<id>urn:sha1:8792468da5e12e77e76e1edf081acf0392abb331</id>
<content type='text'>
This patch adds the ability to be able to save the FPU registers to the
thread struct without giving up (disabling the facility) next time the
process returns to userspace.

This patch optimises the thread copy path (as a result of a fork() or
clone()) so that the parent thread can return to userspace with hot
registers avoiding a possibly pointless reload of FPU register state.

Signed-off-by: Cyril Bur &lt;cyrilbur@gmail.com&gt;
Signed-off-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
</content>
</entry>
<entry>
<title>powerpc: Prepare for splitting giveup_{fpu, altivec, vsx} in two</title>
<updated>2016-03-02T12:34:48Z</updated>
<author>
<name>Cyril Bur</name>
</author>
<published>2016-02-29T06:53:48Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=de2a20aa7237b45d3c14a2505804a8daa95a8f53'/>
<id>urn:sha1:de2a20aa7237b45d3c14a2505804a8daa95a8f53</id>
<content type='text'>
This prepares for the decoupling of saving {fpu,altivec,vsx} registers and
marking {fpu,altivec,vsx} as being unused by a thread.

Currently giveup_{fpu,altivec,vsx}() does both however optimisations to
task switching can be made if these two operations are decoupled.
save_all() will permit the saving of registers to thread structs and leave
threads MSR with bits enabled.

This patch introduces no functional change.

Signed-off-by: Cyril Bur &lt;cyrilbur@gmail.com&gt;
Signed-off-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
</content>
</entry>
<entry>
<title>powerpc: clean up asm/switch_to.h</title>
<updated>2015-12-02T08:34:41Z</updated>
<author>
<name>Anton Blanchard</name>
</author>
<published>2015-10-29T00:44:11Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=d1e1cf2e38def301fde42c1a33f896f974941d7b'/>
<id>urn:sha1:d1e1cf2e38def301fde42c1a33f896f974941d7b</id>
<content type='text'>
Remove a bunch of unnecessary fallback functions and group
things in a more logical way.

Signed-off-by: Anton Blanchard &lt;anton@samba.org&gt;
Signed-off-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
</content>
</entry>
<entry>
<title>powerpc: create flush_all_to_thread()</title>
<updated>2015-12-02T08:34:40Z</updated>
<author>
<name>Anton Blanchard</name>
</author>
<published>2015-10-29T00:44:09Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=579e633e764e6e5f7784b74e7df3e81fe11f40de'/>
<id>urn:sha1:579e633e764e6e5f7784b74e7df3e81fe11f40de</id>
<content type='text'>
Create a single function that flushes everything (FP, VMX, VSX, SPE).
Doing this all at once means we only do one MSR write.

Signed-off-by: Anton Blanchard &lt;anton@samba.org&gt;
Signed-off-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
</content>
</entry>
<entry>
<title>powerpc: create giveup_all()</title>
<updated>2015-12-02T08:34:26Z</updated>
<author>
<name>Anton Blanchard</name>
</author>
<published>2015-10-29T00:44:08Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=c208505900b232ecdc81dee54cb3a032e75d88d6'/>
<id>urn:sha1:c208505900b232ecdc81dee54cb3a032e75d88d6</id>
<content type='text'>
Create a single function that gives everything up (FP, VMX, VSX, SPE).
Doing this all at once means we only do one MSR write.

A context switch microbenchmark using yield():

http://ozlabs.org/~anton/junkcode/context_switch2.c

./context_switch2 --test=yield --fp --altivec --vector 0 0

shows an improvement of 3% on POWER8.

Signed-off-by: Anton Blanchard &lt;anton@samba.org&gt;
[mpe: giveup_all() needs to be EXPORT_SYMBOL'ed]
Signed-off-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
</content>
</entry>
<entry>
<title>powerpc: Add ppc_strict_facility_enable boot option</title>
<updated>2015-12-01T02:52:26Z</updated>
<author>
<name>Anton Blanchard</name>
</author>
<published>2015-10-29T00:44:06Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=3eb5d5888dc68c9b187998ca4249b8b9fa481eeb'/>
<id>urn:sha1:3eb5d5888dc68c9b187998ca4249b8b9fa481eeb</id>
<content type='text'>
Add a boot option that strictly manages the MSR unavailable bits.
This catches kernel uses of FP/Altivec/SPE that would otherwise
corrupt user state.

Signed-off-by: Anton Blanchard &lt;anton@samba.org&gt;
Signed-off-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
</content>
</entry>
</feed>
