kernel.git/arch/powerpc/include/asm/reg.h, branch linux-6.4.y

powerpc: Remove duplicate SPRN_HSRR definitions

2023-04-20T03:21:44Z

There are two copies of these defines. Keep the older ones as they have associated bit definitions. Signed-off-by: Joel Stanley Signed-off-by: Michael Ellerman Link: https://msgid.link/20230405045316.95003-1-joel@jms.id.au

Merge branch 'topic/ppc-kvm' into next

2023-04-04T12:10:32Z

Merge our KVM topic branch to bring some KVM commits into next for wider testing.

KVM: PPC: Enable prefixed instructions for HV KVM and disable for PR KVM

2023-04-03T05:45:59Z

Now that we can read prefixed instructions from a HV KVM guest and emulate prefixed load/store instructions to emulated MMIO locations, we can add HFSCR_PREFIXED into the set of bits that are set in the HFSCR for a HV KVM guest on POWER10, allowing the guest to use prefixed instructions. PR KVM has not yet been extended to handle prefixed instructions in all situations where we might need to emulate them, so prevent the guest from enabling prefixed instructions in the FSCR for now. Reviewed-by: Nicholas Piggin Tested-by: Nicholas Piggin Signed-off-by: Paul Mackerras Tested-by: Sachin Sant Signed-off-by: Michael Ellerman Link: https://msgid.link/ZAgs25dCmLrVkBdU@cleo

powerpc/perf: Properly detect mpc7450 family

2023-03-30T12:35:43Z

Unlike PVR_POWER8, etc ...., PVR_7450 represents a full PVR value and not a family value. To avoid confusion, do like E500 family and define the relevant PVR_VER_xxxx values for the 7450 family: 0x8000 ==> 7450 0x8001 ==> 7455 0x8002 ==> 7447 0x8003 ==> 7447A 0x8004 ==> 7448 And use them to detect 7450 family for perf events. Reported-by: kernel test robot Reported-by: Dan Carpenter Link: https://lore.kernel.org/r/202302260657.7dM9Uwev-lkp@intel.com/ Fixes: ec3eb9d941a9 ("powerpc/perf: Use PVR rather than oprofile field to determine CPU version") Signed-off-by: Christophe Leroy Signed-off-by: Michael Ellerman Link: https://msgid.link/99ca1da2e5a6cf82a8abf4bc034918e500e31781.1677513277.git.christophe.leroy@csgroup.eu

KVM: PPC: Book3S HV: Update LPID allocator init for POWER9, Nested

2022-05-13T11:33:33Z

The LPID allocator init is changed to: - use mmu_lpid_bits rather than hard-coding; - use KVM_MAX_NESTED_GUESTS for nested hypervisors; - not reserve the top LPID on POWER9 and newer CPUs. The reserved LPID is made a POWER7/8-specific detail. Signed-off-by: Nicholas Piggin Reviewed-by: Fabiano Rosas Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220123120043.3586018-3-npiggin@gmail.com

KVM: PPC: Book3S HV: HFSCR[PREFIX] does not exist

2022-05-13T11:33:19Z

This facility is controlled by FSCR only. Reserved bits should not be set in the HFSCR register (although it's likely harmless as this position would not be re-used, and the L0 is forgiving here too). Signed-off-by: Nicholas Piggin Reviewed-by: Fabiano Rosas Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220122105639.3477407-1-npiggin@gmail.com

powerpc/inst: Move ppc_inst_t definition in asm/reg.h

2021-12-09T11:41:21Z

Because of circular inclusion of asm/hw_breakpoint.h, we need to move definition of asm/reg.h outside of inst.h so that asm/hw_breakpoint.h gets it without including asm/inst.h Also remove asm/inst.h from asm/uprobes.h as it's not needed anymore. Signed-off-by: Christophe Leroy Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/4b79f1491118af96b1ac0735e74aeca02ea4c04e.1638208156.git.christophe.leroy@csgroup.eu

powerpc/config: Add CONFIG_BOOKE_OR_40x

2021-12-09T11:41:19Z

We have many functionnalities common to 40x and BOOKE, it leads to many places with #if defined(CONFIG_BOOKE) || defined(CONFIG_40x). We are going to add a few more with KUAP for booke/40x, so create a new symbol which is defined when either BOOKE or 40x is defined. Signed-off-by: Christophe Leroy Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/9a3dbd60924cb25c9f944d3d8205ac5a0d15e229.1634627931.git.christophe.leroy@csgroup.eu

KVM: PPC: Book3S HV Nested: Fix TM softpatch HFAC interrupt emulation

2021-08-25T06:37:17Z

Have the TM softpatch emulation code set up the HFAC interrupt and return -1 in case an instruction was executed with HFSCR bits clear, and have the interrupt exit handler fall through to the HFAC handler. When the L0 is running a nested guest, this ensures the HFAC interrupt is correctly passed up to the L1. The "direct guest" exit handler will turn these into PROGILL program interrupts so functionality in practice will be unchanged. But it's possible an L1 would want to handle these in a different way. Also rearrange the FAC interrupt emulation code to match the HFAC format while here (mainly, adding the FSCR_INTR_CAUSE mask). Signed-off-by: Nicholas Piggin Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20210811160134.904987-5-npiggin@gmail.com

powerpc: Move update_power8_hid0() into its only user

2021-06-16T14:09:11Z

update_power8_hid0() is used only by powernv platform subcore.c Move it there. Signed-off-by: Christophe Leroy Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/37f41d74faa0c66f90b373e243e8b1ee37a1f6fa.1623219019.git.christophe.leroy@csgroup.eu