kernel.git/arch/powerpc/include/asm/opal.h, branch linux-3.18.y

powerpc/powernv: define a standard delay for OPAL_BUSY type retry loops

2018-04-24T07:29:26Z

commit 34dd25de9fe3f60bfdb31b473bf04b28262d0896 upstream. This is the start of an effort to tidy up and standardise all the delays. Existing loops have a range of delay/sleep periods from 1ms to 20ms, and some have no delay. They all loop forever except rtc, which times out after 10 retries, and that uses 10ms delays. So use 10ms as our standard delay. The OPAL maintainer agrees 10ms is a reasonable starting point. The idea is to use the same recipe everywhere, once this is proven to work then it will be documented as an OPAL API standard. Then both firmware and OS can agree, and if a particular call needs something else, then that can be documented with reasoning. This is not the end-all of this effort, it's just a relatively easy change that fixes some existing high latency delays. There should be provision for standardising timeouts and/or interruptible loops where possible, so non-fatal firmware errors don't cause hangs. Signed-off-by: Nicholas Piggin Signed-off-by: Michael Ellerman Cc: Nathan Chancellor Cc: Guenter Roeck Signed-off-by: Greg Kroah-Hartman

powerpc/opal: Add PHB to cxl mode call

2014-10-08T09:15:52Z

This adds the OPAL call to change a PHB into cxl mode. Signed-off-by: Ian Munsie Signed-off-by: Michael Neuling Signed-off-by: Michael Ellerman

powerpc/powernv: Sync OpalPciResetScope with firmware

2014-09-30T07:15:17Z

The names of PCI reset scopes aren't sychronized with firmware. The patch fixes it. Signed-off-by: Gavin Shan Signed-off-by: Michael Ellerman

powerpc/powernv: Sync header with firmware

2014-09-30T07:15:09Z

The patch synchronizes firmware header file (opal.h) for PCI error injection. Signed-off-by: Mike Qiu Signed-off-by: Gavin Shan Signed-off-by: Michael Ellerman

powerpc/powernv: Add OPAL check token call

2014-09-25T13:14:35Z

Currently there is no way to generically check if an OPAL call exists or not from the host kernel. This adds an OPAL call opal_check_token() which tells you if the given token is present in OPAL or not. Signed-off-by: Michael Neuling Signed-off-by: Michael Ellerman

powerpc/powernv: Interface to register/unregister opal dump region

2014-08-13T05:13:45Z

PowerNV platform is capable of capturing host memory region when system crashes (because of host/firmware). We have new OPAL API to register/ unregister memory region to be captured when system crashes. This patch adds support for new API. Also during boot time we register kernel log buffer and unregister before doing kexec. Signed-off-by: Vasant Hegde Signed-off-by: Benjamin Herrenschmidt

powerpc/powernv: Invoke opal call to handle hmi.

2014-08-05T06:33:52Z

When we hit the HMI in Linux, invoke opal call to handle/recover from HMI errors in real mode and then in virtual mode during check_irq_replay() invoke opal_poll_events()/opal_do_notifier() to retrieve HMI event from OPAL and act accordingly. Now that we are ready to handle HMI interrupt directly in linux, remove the HMI interrupt registration with firmware. Signed-off-by: Mahesh Salgaonkar Signed-off-by: Benjamin Herrenschmidt

powerpc/book3s: Add basic infrastructure to handle HMI in Linux.

2014-08-05T06:33:48Z

Handle Hypervisor Maintenance Interrupt (HMI) in Linux. This patch implements basic infrastructure to handle HMI in Linux host. The design is to invoke opal handle hmi in real mode for recovery and set irq_pending when we hit HMI. During check_irq_replay pull opal hmi event and print hmi info on console. Signed-off-by: Mahesh Salgaonkar Signed-off-by: Benjamin Herrenschmidt

powerpc/powernv: Allow to freeze PE

2014-08-05T05:41:52Z

The patch synchronizes header file with firmware to have new OPAL API opal_pci_eeh_freeze_set(), which is used to freeze the specified PE in order to support "compound" PE. Signed-off-by: Gavin Shan Signed-off-by: Benjamin Herrenschmidt

powerpc/powernv: Enable M64 aperatus for PHB3

2014-08-05T05:41:47Z

This patch enables M64 aperatus for PHB3. We already had platform hook (ppc_md.pcibios_window_alignment) to affect the PCI resource assignment done in PCI core so that each PE's M32 resource was built on basis of M32 segment size. Similarly, we're using that for M64 assignment on basis of M64 segment size. * We're using last M64 BAR to cover M64 aperatus, and it's shared by all 256 PEs. * We don't support P7IOC yet. However, some function callbacks are added to (struct pnv_phb) so that we can reuse them on P7IOC in future. * PE, corresponding to PCI bus with large M64 BAR device attached, might span multiple M64 segments. We introduce "compound" PE to cover the case. The compound PE is a list of PEs and the master PE is used as before. The slave PEs are just for MMIO isolation. Signed-off-by: Guo Chao Signed-off-by: Benjamin Herrenschmidt