<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/arch/parisc/kernel/syscall.S, branch linux-5.16.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.16.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.16.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2021-12-21T20:07:39Z</updated>
<entry>
<title>parisc: Correct completer in lws start</title>
<updated>2021-12-21T20:07:39Z</updated>
<author>
<name>John David Anglin</name>
</author>
<published>2021-12-21T18:21:22Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=8f66fce0f46560b9e910787ff7ad0974441c4f9c'/>
<id>urn:sha1:8f66fce0f46560b9e910787ff7ad0974441c4f9c</id>
<content type='text'>
The completer in the "or,ev %r1,%r30,%r30" instruction is reversed, so we are
not clipping the LWS number when we are called from a 32-bit process (W=0).
We need to nulify the following depdi instruction when the least-significant
bit of %r30 is 1.

If the %r20 register is not clipped, a user process could perform a LWS call
that would branch to an undefined location in the kernel and potentially crash
the machine.

Signed-off-by: John David Anglin &lt;dave.anglin@bell.net&gt;
Cc: stable@vger.kernel.org # 4.19+
Signed-off-by: Helge Deller &lt;deller@gmx.de&gt;
</content>
</entry>
<entry>
<title>parisc: Fix extraction of hash lock bits in syscall.S</title>
<updated>2021-11-22T06:37:31Z</updated>
<author>
<name>John David Anglin</name>
</author>
<published>2021-11-19T21:18:47Z</published>
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<id>urn:sha1:df2ffeda6370a77011902e7c9d7a1eb1cbffed4f</id>
<content type='text'>
The extru instruction leaves the most significant 32 bits of the target
register in an undefined state on PA 2.0 systems. If any of these bits
are nonzero, this will break the calculation of the lock pointer.

Fix by using extrd,u instruction via extru_safe macro on 64-bit kernels.

Signed-off-by: John David Anglin &lt;dave.anglin@bell.net&gt;
Signed-off-by: Helge Deller &lt;deller@gmx.de&gt;
</content>
</entry>
<entry>
<title>parisc: Don't disable interrupts in cmpxchg and futex operations</title>
<updated>2021-11-04T10:21:20Z</updated>
<author>
<name>Dave Anglin</name>
</author>
<published>2021-11-03T11:49:32Z</published>
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<id>urn:sha1:7e992711dddbdb1c27d077432d8440fefd44819f</id>
<content type='text'>
I no longer think interrupts can be disabled in the futex and cmpxchg
operations because of COW breaks.  This not ideal but I suspect it's the
best we can do.

For the cmpxchg operations in syscall.S, we rely on the code to not
schedule off the gateway page.  For the futex, I added code to disable
preemption.

So far, I haven't seen the warnings with the attached change but the
change is only lightly tested.

Signed-off-by: Dave Anglin &lt;dave.anglin@bell.net&gt;
Signed-off-by: Helge Deller &lt;deller@gmx.de&gt;
</content>
</entry>
<entry>
<title>parisc: Use PRIV_USER in syscall.S</title>
<updated>2021-11-01T06:36:00Z</updated>
<author>
<name>Helge Deller</name>
</author>
<published>2021-10-17T13:23:53Z</published>
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<id>urn:sha1:fdc9e4e0ef897351f953c3a37e644670e3195926</id>
<content type='text'>
Signed-off-by: Helge Deller &lt;deller@gmx.de&gt;
</content>
</entry>
<entry>
<title>parisc: Move thread_info into task struct</title>
<updated>2021-11-01T06:35:59Z</updated>
<author>
<name>Helge Deller</name>
</author>
<published>2021-10-15T08:41:03Z</published>
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<id>urn:sha1:2214c0e77259b420402e279e9ab4277ef320d371</id>
<content type='text'>
This implements the CONFIG_THREAD_INFO_IN_TASK option.

With this change:
- before thread_info was part of the stack and located at the beginning of the stack
- now the thread_info struct is moved and located inside the task_struct structure
- the stack is allocated and handled like the major other platforms
- drop the cpu field of thread_info and use instead the one in task_struct

Signed-off-by: Helge Deller &lt;deller@gmx.de&gt;
Signed-off-by: Sven Schnelle &lt;svens@stackframe.org&gt;
</content>
</entry>
<entry>
<title>parisc: syscalls: switch to generic syscalltbl.sh</title>
<updated>2021-04-27T07:43:56Z</updated>
<author>
<name>Masahiro Yamada</name>
</author>
<published>2021-03-01T14:58:22Z</published>
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<id>urn:sha1:df86ddbb9189d4fe6fe2c143d244e1121b57eb50</id>
<content type='text'>
Many architectures duplicate similar shell scripts.

This commit converts parisc to use scripts/syscalltbl.sh. This also
unifies syscall_table_64.h and syscall_table_c32.h.

Signed-off-by: Masahiro Yamada &lt;masahiroy@kernel.org&gt;
Acked-by: Helge Deller &lt;deller@gmx.de&gt;
Signed-off-by: Helge Deller &lt;deller@gmx.de&gt;
</content>
</entry>
<entry>
<title>parisc: Switch to more fine grained lws locks</title>
<updated>2020-10-15T06:10:39Z</updated>
<author>
<name>John David Anglin</name>
</author>
<published>2020-10-02T19:21:41Z</published>
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<id>urn:sha1:53a42b6324b8ddce1e9d2f34da2ca68ef21c2084</id>
<content type='text'>
Increase the number of lws locks to 256 entries (instead of 16) and
choose lock entry based on bits 3-11 (instead of 4-7) of the relevant
address.  With this change we archieve more fine-grained locking in
futex syscalls and thus reduce the number of possible stalls.

Signed-off-by: John David Anglin &lt;dave.anglin@bell.net&gt;
Signed-off-by: Helge Deller &lt;deller@gmx.de&gt;
</content>
</entry>
<entry>
<title>Revert "parisc: Revert "Release spinlocks using ordered store""</title>
<updated>2020-07-28T16:56:14Z</updated>
<author>
<name>Helge Deller</name>
</author>
<published>2020-07-28T16:56:14Z</published>
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<id>urn:sha1:157e9afcc4fa25068b0e8743bc254a9b56010e13</id>
<content type='text'>
This reverts commit 86d4d068df573a8c2105554624796c086d6bec3d.

Signed-off-by: Helge Deller &lt;deller@gmx.de&gt;
Cc: &lt;stable@vger.kernel.org&gt; # v5.0+
</content>
</entry>
<entry>
<title>Revert "parisc: Use ldcw instruction for SMP spinlock release barrier"</title>
<updated>2020-07-28T16:54:40Z</updated>
<author>
<name>Helge Deller</name>
</author>
<published>2020-07-28T16:54:40Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=6e9f06ee6c9566f3606d93182ac8f803a148504b'/>
<id>urn:sha1:6e9f06ee6c9566f3606d93182ac8f803a148504b</id>
<content type='text'>
This reverts commit 9e5c602186a692a7e848c0da17aed40f49d30519.
No need to use the ldcw instruction as SMP spinlock release barrier.
Revert it to gain back speed again.

Signed-off-by: Helge Deller &lt;deller@gmx.de&gt;
Cc: &lt;stable@vger.kernel.org&gt; # v5.2+
</content>
</entry>
<entry>
<title>Revert "parisc: Drop LDCW barrier in CAS code when running UP"</title>
<updated>2020-07-28T16:52:58Z</updated>
<author>
<name>Helge Deller</name>
</author>
<published>2020-07-28T16:52:58Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=462fb756c7de1ffe5bc6099149136031c2d9c02a'/>
<id>urn:sha1:462fb756c7de1ffe5bc6099149136031c2d9c02a</id>
<content type='text'>
This reverts commit e6eb5fe9123f05dcbf339ae5c0b6d32fcc0685d5.
We need to optimize it differently. A follow up patch will correct it.

Signed-off-by: Helge Deller &lt;deller@gmx.de&gt;
Cc: &lt;stable@vger.kernel.org&gt; # v5.2+
</content>
</entry>
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