<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/arch/parisc/include/asm, branch linux-5.16.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.16.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.16.y'/>
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<updated>2022-04-08T12:06:34Z</updated>
<entry>
<title>parisc: Fix handling off probe non-access faults</title>
<updated>2022-04-08T12:06:34Z</updated>
<author>
<name>John David Anglin</name>
</author>
<published>2022-03-09T21:14:36Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=3a354b5a1db54284b94bb768077c760a8b938ec1'/>
<id>urn:sha1:3a354b5a1db54284b94bb768077c760a8b938ec1</id>
<content type='text'>
[ Upstream commit e00b0a2ab8ec019c344e53bfc76e31c18bb587b7 ]

Currently, the parisc kernel does not fully support non-access TLB
fault handling for probe instructions. In the fast path, we set the
target register to zero if it is not a shadowed register. The slow
path is not implemented, so we call do_page_fault. The architecture
indicates that non-access faults should not cause a page fault from
disk.

This change adds to code to provide non-access fault support for
probe instructions. It also modifies the handling of faults on
userspace so that if the address lies in a valid VMA and the access
type matches that for the VMA, the probe target register is set to
one. Otherwise, the target register is set to zero.

This was done to make probe instructions more useful for userspace.
Probe instructions are not very useful if they set the target register
to zero whenever a page is not present in memory. Nominally, the
purpose of the probe instruction is determine whether read or write
access to a given address is allowed.

This fixes a problem in function pointer comparison noticed in the
glibc testsuite (stdio-common/tst-vfprintf-user-type). The same
problem is likely in glibc (_dl_lookup_address).

V2 adds flush and lpa instruction support to handle_nadtlb_fault.

Signed-off-by: John David Anglin &lt;dave.anglin@bell.net&gt;
Signed-off-by: Helge Deller &lt;deller@gmx.de&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>parisc: Show error if wrong 32/64-bit compiler is being used</title>
<updated>2022-02-23T11:05:46Z</updated>
<author>
<name>Helge Deller</name>
</author>
<published>2022-02-13T21:29:25Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=96b795abc7e6e28ea66465f079fcadba12e33fd9'/>
<id>urn:sha1:96b795abc7e6e28ea66465f079fcadba12e33fd9</id>
<content type='text'>
commit b160628e9ebcdc85d0db9d7f423c26b3c7c179d0 upstream.

It happens quite often that people use the wrong compiler to build the
kernel:

make ARCH=parisc   -&gt; builds the 32-bit kernel
make ARCH=parisc64 -&gt; builds the 64-bit kernel

This patch adds a sanity check which errors out with an instruction how
use the correct ARCH= option.

Signed-off-by: Helge Deller &lt;deller@gmx.de&gt;
Cc: stable@vger.kernel.org # v5.15+
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>parisc: Fix lpa and lpa_user defines</title>
<updated>2022-01-27T11:02:45Z</updated>
<author>
<name>John David Anglin</name>
</author>
<published>2021-12-22T16:01:31Z</published>
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<id>urn:sha1:f5acbab448f82875761eaca10cd401a12405f55d</id>
<content type='text'>
commit db19c6f1a2a353cc8dec35b4789733a3cf6e2838 upstream.

While working on the rewrite to the light-weight syscall and futex code, I
experimented with using a hash index based on the user physical address of
atomic variable. This exposed two problems with the lpa and lpa_user defines.

Because of the copy instruction, the pa argument needs to be an early clobber
argument. This prevents gcc from allocating the va and pa arguments to the same
register.

Secondly, the lpa instruction can cause a page fault so we need to catch
exceptions.

Signed-off-by: John David Anglin &lt;dave.anglin@bell.net&gt;
Fixes: 116d753308cf ("parisc: Use lpa instruction to load physical addresses in driver code")
Signed-off-by: Helge Deller &lt;deller@gmx.de&gt;
Cc: stable@vger.kernel.org # v5.2+
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>parisc: Fix mask used to select futex spinlock</title>
<updated>2021-12-21T20:15:59Z</updated>
<author>
<name>John David Anglin</name>
</author>
<published>2021-12-21T18:33:16Z</published>
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<id>urn:sha1:d3a5a68cff47f6eead84504c3c28376b85053242</id>
<content type='text'>
The address bits used to select the futex spinlock need to match those used in
the LWS code in syscall.S. The mask 0x3f8 only selects 7 bits.  It should
select 8 bits.

This change fixes the glibc nptl/tst-cond24 and nptl/tst-cond25 tests.

Signed-off-by: John David Anglin &lt;dave.anglin@bell.net&gt;
Fixes: 53a42b6324b8 ("parisc: Switch to more fine grained lws locks")
Cc: stable@vger.kernel.org # 5.10+
Signed-off-by: Helge Deller &lt;deller@gmx.de&gt;
</content>
</entry>
<entry>
<title>Merge tag 'folio-5.16b' of git://git.infradead.org/users/willy/pagecache</title>
<updated>2021-11-25T18:13:56Z</updated>
<author>
<name>Linus Torvalds</name>
</author>
<published>2021-11-25T18:13:56Z</published>
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<id>urn:sha1:79941493ff3e75219fd1d37a09b46a604e9e55ac</id>
<content type='text'>
Pull folio fixes from Matthew Wilcox:
 "In the course of preparing the folio changes for iomap for next merge
  window, we discovered some problems that would be nice to address now:

   - Renaming multi-page folios to large folios.

     mapping_multi_page_folio_support() is just a little too long, so we
     settled on mapping_large_folio_support(). That meant renaming, eg
     folio_test_multi() to folio_test_large().

     Rename AS_THP_SUPPORT to match

   - I hadn't included folio wrappers for zero_user_segments(), etc.
     Also, multi-page^W^W large folio support is now independent of
     CONFIG_TRANSPARENT_HUGEPAGE, so machines with HIGHMEM always need
     to fall back to the out-of-line zero_user_segments().

     Remove FS_THP_SUPPORT to match

   - The build bots finally got round to telling me that I missed a
     couple of architectures when adding flush_dcache_folio(). Christoph
     suggested that we just add linux/cacheflush.h and not rely on
     asm-generic/cacheflush.h"

* tag 'folio-5.16b' of git://git.infradead.org/users/willy/pagecache:
  mm: Add functions to zero portions of a folio
  fs: Rename AS_THP_SUPPORT and mapping_thp_support
  fs: Remove FS_THP_SUPPORT
  mm: Remove folio_test_single
  mm: Rename folio_test_multi to folio_test_large
  Add linux/cacheflush.h
</content>
</entry>
<entry>
<title>parisc: Provide an extru_safe() macro to extract unsigned bits</title>
<updated>2021-11-22T06:37:31Z</updated>
<author>
<name>Helge Deller</name>
</author>
<published>2021-11-19T21:16:37Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=169d1a4a2adb2c246396c56aa2f9eec3868546f1'/>
<id>urn:sha1:169d1a4a2adb2c246396c56aa2f9eec3868546f1</id>
<content type='text'>
The extru instruction leaves the most significant 32 bits of the
target register in an undefined state on PA 2.0 systems.
Provide a macro to safely use extru on 32- and 64-bit machines.

Suggested-by: John David Anglin &lt;dave.anglin@bell.net&gt;
Signed-off-by: Helge Deller &lt;deller@gmx.de&gt;
</content>
</entry>
<entry>
<title>Revert "parisc: Reduce sigreturn trampoline to 3 instructions"</title>
<updated>2021-11-18T08:02:32Z</updated>
<author>
<name>Helge Deller</name>
</author>
<published>2021-11-17T10:05:07Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=79df39d535c7a3770856fe9f5aba8c0ad1eebdb6'/>
<id>urn:sha1:79df39d535c7a3770856fe9f5aba8c0ad1eebdb6</id>
<content type='text'>
This reverts commit e4f2006f1287e7ea17660490569cff323772dac4.

This patch shows problems with signal handling. Revert it for now.

Signed-off-by: Helge Deller &lt;deller@gmx.de&gt;
Cc: &lt;stable@vger.kernel.org&gt; # v5.15
</content>
</entry>
<entry>
<title>parisc: Wrap assembler related defines inside __ASSEMBLY__</title>
<updated>2021-11-18T08:02:00Z</updated>
<author>
<name>Helge Deller</name>
</author>
<published>2021-11-16T12:12:21Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=4017b230c960c9d6c6a19e52bf3df01222dc7737'/>
<id>urn:sha1:4017b230c960c9d6c6a19e52bf3df01222dc7737</id>
<content type='text'>
Building allmodconfig shows errors in the gpu/drm/msm snapdragon drivers,
because a COND() define is used there which conflicts with the COND() for
PA-RISC assembly.  Although the snapdragon driver isn't relevant for parisc, it
is nevertheless compiled when CONFIG_COMPILE_TEST is defined.

Move the COND() define and other PA-RISC mnemonics inside the #ifdef
__ASSEMBLY__ part to avoid this conflict.

Signed-off-by: Helge Deller &lt;deller@gmx.de&gt;
Reported-by: kernel test robot &lt;lkp@intel.com&gt;
</content>
</entry>
<entry>
<title>parisc: Include stringify.h to avoid build error in crypto/api.c</title>
<updated>2021-11-18T08:01:36Z</updated>
<author>
<name>Helge Deller</name>
</author>
<published>2021-11-15T16:34:50Z</published>
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<id>urn:sha1:4d7804d201f2588469798faaab7b54caeb67410b</id>
<content type='text'>
Include stringify.h to avoid this build error:
 arch/parisc/include/asm/jump_label.h: error: expected ':' before '__stringify'
 arch/parisc/include/asm/jump_label.h: error: label 'l_yes' defined but not used [-Werror=unused-label]

Signed-off-by: Helge Deller &lt;deller@gmx.de&gt;
Reported-by: kernel test robot &lt;lkp@intel.com&gt;
</content>
</entry>
<entry>
<title>Add linux/cacheflush.h</title>
<updated>2021-11-17T15:36:15Z</updated>
<author>
<name>Matthew Wilcox (Oracle)</name>
</author>
<published>2021-11-06T21:13:35Z</published>
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<id>urn:sha1:522a0032af005502507f5f81ae64fdcc82b5d068</id>
<content type='text'>
Many architectures do not include asm-generic/cacheflush.h, so turn
the includes on their head and add linux/cacheflush.h which includes
asm/cacheflush.h.

Move the flush_dcache_folio() declaration from asm-generic/cacheflush.h
to linux/cacheflush.h and change linux/highmem.h to include
linux/cacheflush.h instead of asm/cacheflush.h so that all necessary
places will see flush_dcache_folio().

More functions should have their default implementations moved in the
future, but those are for follow-on patches.  This fixes csky, sparc and
sparc64 which were missed in the commit which added flush_dcache_folio().

Fixes: 08b0b0059bf1 ("mm: Add flush_dcache_folio()")
Suggested-by: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Matthew Wilcox (Oracle) &lt;willy@infradead.org&gt;
Acked-by: Geert Uytterhoeven &lt;geert@linux-m68k.org&gt;
</content>
</entry>
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