kernel.git/arch/mips/mm/cache.c, branch linux-2.6.28.y

[MIPS] Fix WARNING: at kernel/smp.c:290

2008-09-05T20:24:11Z

trap_init issues flush_icache_range(), which uses ipi functions to get icache flushing done on all cpus. But this is done before interrupts are enabled and caused WARN_ON messages. This changeset introduces a new local_flush_icache_range() and uses it before interrupts (and additional CPUs) are enabled to avoid this problem. Signed-off-by: Thomas Bogendoerfer Signed-off-by: Ralf Baechle

[MIPS] Allow setting of the cache attribute at run time.

2008-04-28T16:14:25Z

Slightly tacky, but there is a precedent in the sparc archirecture code. Signed-off-by: Chris Dearman Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle

[MIPS] Handle aliases in vmalloc correctly.

2008-04-07T21:31:04Z

flush_cache_vmap / flush_cache_vunmap were calling flush_cache_all which - having been deprecated - turned into a nop ... Signed-off-by: Ralf Baechle

[MIPS] Fix loads of section missmatches

2008-03-12T14:14:41Z

Signed-off-by: Ralf Baechle

[MIPS] Fix buggy invocations of kmap_coherent()

2008-02-19T17:01:31Z

kmap_coherent will only work correctly if the page it is called on is not marked dirty. If it's dirty the kernel address of the page should be used instead of a temporary mapping. Signed-off-by: Ralf Baechle

Remove dma_cache_(wback|inv|wback_inv) functions

2007-10-17T15:42:57Z

dma_cache_(wback|inv|wback_inv) were the earliest attempt on a generalized cache managment API for I/O purposes. Originally it was basically the raw MIPS low level cache API exported to the entire world. The API has suffered from a lack of documentation, was not very widely used unlike it's more modern brothers and can easily be replaced by dma_cache_sync. So remove it rsp. turn the surviving bits back into an arch private API, as discussed on linux-arch. Signed-off-by: Ralf Baechle Acked-by: Paul Mundt Acked-by: Paul Mackerras Acked-by: David S. Miller Acked-by: Kyle McMartin Acked-by: Haavard Skinnemoen Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.

2007-10-11T22:46:05Z

It may not be perfect yet but the SB1 code is badly borken and has horrible performance issues. Downside: This seriously breaks support for pass 1 parts of the BCM1250 where indexed cacheops don't work quite reliable but I seem to be the last one on the planet with a pass 1 part anyway. Signed-off-by: Ralf Baechle

[MIPS] Hook for platforms to define cachability of /dev/mem regions

2007-07-10T16:32:56Z

Signed-off-by: Ralf Baechle

[MIPS] Remove unused argument from kunmap_coherent().

2007-04-27T15:20:24Z

Signed-off-by: Ralf Baechle

[MIPS] Implement flush_anon_page().

2007-03-24T17:01:49Z

Signed-off-by: Ralf Baechle