kernel.git/arch/mips/kvm/emulate.c, branch linux-4.9.y

KVM: MIPS: Precalculate MMIO load resume PC

2016-10-26T11:43:55Z

The advancing of the PC when completing an MMIO load is done before re-entering the guest, i.e. before restoring the guest ASID. However if the load is in a branch delay slot it may need to access guest code to read the prior branch instruction. This isn't safe in TLB mapped code at the moment, nor in the future when we'll access unmapped guest segments using direct user accessors too, as it could read the branch from host user memory instead. Therefore calculate the resume PC in advance while we're still in the right context and save it in the new vcpu->arch.io_pc (replacing the no longer needed vcpu->arch.pending_load_cause), and restore it on MMIO completion. Fixes: e685c689f3a8 ("KVM/MIPS32: Privileged instruction/target branch emulation.") Signed-off-by: James Hogan Cc: Paolo Bonzini Cc: "Radim Krčmář Cc: Ralf Baechle Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Cc: # 3.10.x- Signed-off-by: Paolo Bonzini

KVM: MIPS: Make ERET handle ERL before EXL

2016-10-26T11:43:48Z

The ERET instruction to return from exception is used for returning from exception level (Status.EXL) and error level (Status.ERL). If both bits are set however we should be returning from ERL first, as ERL can interrupt EXL, for example when an NMI is taken. KVM however checks EXL first. Fix the order of the checks to match the pseudocode in the instruction set manual. Fixes: e685c689f3a8 ("KVM/MIPS32: Privileged instruction/target branch emulation.") Signed-off-by: James Hogan Cc: Paolo Bonzini Cc: "Radim Krčmář Cc: Ralf Baechle Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Cc: # 3.10.x- Signed-off-by: Paolo Bonzini

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

2016-10-15T16:26:12Z

Pull MIPS updates from Ralf Baechle: "This is the main MIPS pull request for 4.9: MIPS core arch code: - traps: 64bit kernels should read CP0_EBase 64bit - traps: Convert ebase to KSEG0 - c-r4k: Drop bc_wback_inv() from icache flush - c-r4k: Split user/kernel flush_icache_range() - cacheflush: Use __flush_icache_user_range() - uprobes: Flush icache via kernel address - KVM: Use __local_flush_icache_user_range() - c-r4k: Fix flush_icache_range() for EVA - Fix -mabi=64 build of vdso.lds - VDSO: Drop duplicated -I*/-E* aflags - tracing: move insn_has_delay_slot to a shared header - tracing: disable uprobe/kprobe on compact branch instructions - ptrace: Fix regs_return_value for kernel context - Squash lines for simple wrapper functions - Move identification of VP(E) into proc.c from smp-mt.c - Add definitions of SYNC barrierstype values - traps: Ensure full EBase is written - tlb-r4k: If there are wired entries, don't use TLBINVF - Sanitise coherentio semantics - dma-default: Don't check hw_coherentio if device is non-coherent - Support per-device DMA coherence - Adjust MIPS64 CAC_BASE to reflect Config.K0 - Support generating Flattened Image Trees (.itb) - generic: Introduce generic DT-based board support - generic: Convert SEAD-3 to a generic board - Enable hardened usercopy - Don't specify STACKPROTECTOR in defconfigs Octeon: - Delete dead code and files across the platform. - Change to use all memory into use by default. - Rename upper case variables in setup code to lowercase. - Delete legacy hack for broken bootloaders. - Leave maintaining the link state to the actual ethernet/PHY drivers. - Add DTS for D-Link DSR-500N. - Fix PCI interrupt routing on D-Link DSR-500N. Pistachio: - Remove ANDROID_TIMED_OUTPUT from defconfig TX39xx: - Move GPIO setup from .mem_setup() to .arch_init() - Convert to Common Clock Framework TX49xx: - Move GPIO setup from .mem_setup() to .arch_init() - Convert to Common Clock Framework txx9wdt: - Add missing clock (un)prepare calls for CCF BMIPS: - Add PW, GPIO SDHCI and NAND device node names - Support APPENDED_DTB - Add missing bcm97435svmb to DT_NONE - Rename bcm96358nb4ser to bcm6358-neufbox4-sercom - Add DT examples for BCM63268, BCM3368 and BCM6362 - Add support for BCM3368 and BCM6362 PCI - Reduce stack frame usage - Use struct list_head lists - Support for CONFIG_PCI_DOMAINS_GENERIC - Make pcibios_set_cache_line_size an initcall - Inline pcibios_assign_all_busses - Split pci.c into pci.c & pci-legacy.c - Introduce CONFIG_PCI_DRIVERS_LEGACY - Support generic drivers CPC - Convert bare 'unsigned' to 'unsigned int' - Avoid lock when MIPS CM >= 3 is present GIC: - Delete unused file smp-gic.c mt7620: - Delete unnecessary assignment for the field "owner" from PCI BCM63xx: - Let clk_disable() return immediately if clk is NULL pm-cps: - Change FSB workaround to CPU blacklist - Update comments on barrier instructions - Use MIPS standard lightweight ordering barrier - Use MIPS standard completion barrier - Remove selection of sync types - Add MIPSr6 CPU support - Support CM3 changes to Coherence Enable Register SMP: - Wrap call to mips_cpc_lock_other in mips_cm_lock_other - Introduce mechanism for freeing and allocating IPIs cpuidle: - cpuidle-cps: Enable use with MIPSr6 CPUs. SEAD3: - Rewrite to use DT and generic kernel feature. USB: - host: ehci-sead3: Remove SEAD-3 EHCI code FBDEV: - cobalt_lcdfb: Drop SEAD3 support dt-bindings: - Document a binding for simple ASCII LCDs auxdisplay: - img-ascii-lcd: driver for simple ASCII LCD displays irqchip i8259: - i8259: Add domain before mapping parent irq - i8259: Allow platforms to override poll function - i8259: Remove unused i8259A_irq_pending Malta: - Rewrite to use DT of/platform: - Probe "isa" busses by default CM: - Print CM error reports upon bus errors Module: - Migrate exception table users off module.h and onto extable.h - Make various drivers explicitly non-modular: - Audit and remove any unnecessary uses of module.h mailmap: - Canonicalize to Qais' current email address. Documentation: - MIPS supports HAVE_REGS_AND_STACK_ACCESS_API Loongson1C: - Add CPU support for Loongson1C - Add board support - Add defconfig - Add RTC support for Loongson1C board All this except one Documentation fix has sat in linux-next and has survived Imagination's automated build test system" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (127 commits) Documentation: MIPS supports HAVE_REGS_AND_STACK_ACCESS_API MIPS: ptrace: Fix regs_return_value for kernel context MIPS: VDSO: Drop duplicated -I*/-E* aflags MIPS: Fix -mabi=64 build of vdso.lds MIPS: Enable hardened usercopy MIPS: generic: Convert SEAD-3 to a generic board MIPS: generic: Introduce generic DT-based board support MIPS: Support generating Flattened Image Trees (.itb) MIPS: Adjust MIPS64 CAC_BASE to reflect Config.K0 MIPS: Print CM error reports upon bus errors MIPS: Support per-device DMA coherence MIPS: dma-default: Don't check hw_coherentio if device is non-coherent MIPS: Sanitise coherentio semantics MIPS: PCI: Support generic drivers MIPS: PCI: Introduce CONFIG_PCI_DRIVERS_LEGACY MIPS: PCI: Split pci.c into pci.c & pci-legacy.c MIPS: PCI: Inline pcibios_assign_all_busses MIPS: PCI: Make pcibios_set_cache_line_size an initcall MIPS: PCI: Support for CONFIG_PCI_DOMAINS_GENERIC MIPS: PCI: Use struct list_head lists ...

MIPS: kvm: Audit and remove any unnecessary uses of module.h

2016-10-04T23:31:20Z

Historically a lot of these existed because we did not have a distinction between what was modular code and what was providing support to modules via EXPORT_SYMBOL and friends. That changed when we forked out support for the latter into the export.h file. This means we should be able to reduce the usage of module.h in code that is obj-y Makefile or bool Kconfig. In the case of kvm where it is modular, we can extend that to also include files that are building basic support functionality but not related to loading or registering the final module; such files also have no need whatsoever for module.h The advantage in removing such instances is that module.h itself sources about 15 other headers; adding significantly to what we feed cpp, and it can obscure what headers we are effectively using. Since module.h was the source for init.h (for __init) and for export.h (for EXPORT_SYMBOL) we consider each instance for the presence of either and replace as needed. In this case, we did not need to add either to any files. Signed-off-by: Paul Gortmaker Acked-by: James Hogan Acked-by: Paolo Bonzini Cc: "Radim Krčmář" Cc: kvm@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14036/ Signed-off-by: Ralf Baechle

KVM: MIPS: Drop dubious EntryHi optimisation

2016-09-29T11:40:12Z

There exists a slightly dubious optimisation in the implementation of the MIPS KVM EntryHi emulation which skips TLB invalidation if the EntryHi points to an address in the guest KSeg0 region, intended to catch guest TLB invalidations where the ASID is almost immediately restored to the previous value. Now that we perform lazy host ASID regeneration for guest user mode when the guest ASID changes we should be able to drop the optimisation without a significant impact (only the extra TLB refills for the small amount of code while the TLB is being invalidated). Signed-off-by: James Hogan Cc: Paolo Bonzini Cc: "Radim Krčmář" Cc: Ralf Baechle Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org

KVM: MIPS: Invalidate TLB by regenerating ASIDs

2016-09-29T11:40:12Z

Invalidate host TLB mappings when the guest ASID is changed by regenerating ASIDs, rather than flushing the entire host TLB except entries in the guest KSeg0 range. For the guest kernel mode ASID we regenerate on the spot when the guest ASID is changed, as that will always take place while the guest is in kernel mode. However when the guest invalidates TLB entries the ASID will often by changed temporarily as part of writing EntryHi without the guest returning to user mode in between. We therefore regenerate the user mode ASID lazily before entering the guest in user mode, if and only if the guest ASID has actually changed since the last guest user mode entry. Signed-off-by: James Hogan Cc: Paolo Bonzini Cc: "Radim Krčmář" Cc: Ralf Baechle Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org

KVM: MIPS: Drop other CPU ASIDs on guest MMU changes

2016-09-29T11:39:30Z

When a guest TLB entry is replaced by TLBWI or TLBWR, we only invalidate TLB entries on the local CPU. This doesn't work correctly on an SMP host when the guest is migrated to a different physical CPU, as it could pick up stale TLB mappings from the last time the vCPU ran on that physical CPU. Therefore invalidate both user and kernel host ASIDs on other CPUs, which will cause new ASIDs to be generated when it next runs on those CPUs. We're careful only to do this if the TLB entry was already valid, and only for the kernel ASID where the virtual address it mapped is outside of the guest user address range. Signed-off-by: James Hogan Cc: Paolo Bonzini Cc: "Radim Krčmář" Cc: Ralf Baechle Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Cc: # 3.10.x-

MIPS: KVM: Propagate kseg0/mapped tlb fault errors

2016-08-12T10:01:30Z

Propagate errors from kvm_mips_handle_kseg0_tlb_fault() and kvm_mips_handle_mapped_seg_tlb_fault(), usually triggering an internal error since they normally indicate the guest accessed bad physical memory or the commpage in an unexpected way. Fixes: 858dd5d45733 ("KVM/MIPS32: MMU/TLB operations for the Guest.") Fixes: e685c689f3a8 ("KVM/MIPS32: Privileged instruction/target branch emulation.") Signed-off-by: James Hogan Cc: Paolo Bonzini Cc: "Radim Krčmář" Cc: Ralf Baechle Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Cc: # 3.10.x- Signed-off-by: Radim Krčmář

MIPS: KVM: Sign extend MFC0/RDHWR results

2016-08-01T16:42:25Z

When emulating MFC0 instructions to load 32-bit values from guest COP0 registers and the RDHWR instruction to read the CC (Count) register, sign extend the result to comply with the MIPS64 architecture. The result must be in canonical 32-bit form or the guest may malfunction. Signed-off-by: James Hogan Cc: Paolo Bonzini Cc: "Radim Krčmář" Cc: Ralf Baechle Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Signed-off-by: Paolo Bonzini

MIPS: KVM: Decode RDHWR more strictly

2016-07-05T14:09:18Z

When KVM emulates the RDHWR instruction, decode the instruction more strictly. The rs field (bits 25:21) should be zero, as should bits 10:9. Bits 8:6 is the register select field in MIPSr6, so we aren't strict about those bits (no other operations should use that encoding space). Signed-off-by: James Hogan Cc: Paolo Bonzini Cc: Radim KrÄmÃ¡Å™ Cc: Ralf Baechle Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Signed-off-by: Paolo Bonzini