kernel.git/arch/mips/kernel/traps.c, branch linux-2.6.34.y

MIPS: Use CKSEG1ADDR for uncached handler

2010-04-30T19:52:48Z

"MIPS: Calculate proper ebase value for 64-bit kernels" 9af43ea080dd5d6c7b34f38261780e5dd43537bc (lmo) rsp. f6be75d03c8870be91e6e2a195648ece04b6bb16 (kernel.org) broke some 64-bit MIPS systems. Before this we were using XKPHYS/cached as ebase and computed the uncached xphsys/unchached address for that area. After that commit ebase became a 32-bit compat address and convert does not work anymore. We now should use CKSEG1 for this. CKSEG1ADDR does just that in 32-bit and 64-bit. Signed-off-by: Sebastian Andrzej Siewior To: Ralf Baechle Patchwork: http://patchwork.linux-mips.org/patch/1149/ Signed-off-by: Ralf Baechle

MIPS: die() does not call die notifier chain

2010-04-30T19:52:45Z

The MIPS implementation of die() forgets to call notify_die() and thus notifiers registered via register_die_notifier() are not called. This results in kgdb not being activated on exceptions. The only subtlety is that notify_die declares its regs argument w/o const, so the const had to be removed from mips die() as well. [Ralf: Fixed build error for SGI IP22 and IP28 platforms.] Signed-off-by: Yury Polyanskiy Cc: linux-mips@linux-mips.org Patchworks: http://patchwork.linux-mips.org/patch/1142/ Acked-by: Jason Wessel Signed-off-by: Ralf Baechle ---

MIPS: Calculate proper ebase value for 64-bit kernels

2010-04-12T16:26:22Z

The ebase is relative to CKSEG0 not CAC_BASE. On a 32-bit kernel they are the same thing, for a 64-bit kernel they are not. It happens to kind of work on a 64-bit kernel as they both reference the same physical memory. However since the CPU uses the CKSEG0 base, determining if a J instruction will reach always gives the wrong result unless we use the same number the CPU uses. Signed-off-by: David Daney To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1093/ Signed-off-by: Ralf Baechle

MIPS: Deal with larger physical offsets

2010-02-27T11:53:19Z

AR7 has a larger physical offset than other MIPS based systems and therefore needs to setup its handlers beyond the usual KSEG0 range. When running the kernel in mapped mode this modification is also required. Remove function comment which is now incorrect. Signed-off-by: David Daney Signed-off-by: Eugene Konev Signed-off-by: Florian Fainelli To: linux-mips@linux-mips.org To: Thomas Bogendoerfer Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/889/ Patchwork: http://patchwork.linux-mips.org/patch/932/ Signed-off-by: Ralf Baechle

MIPS: Annotate set_except_vector with __init

2010-02-27T11:53:19Z

All call sites of set_except_vector are already annotated with __init, so annotate that one too. Signed-off-by: Regards, Florian Fainelli To: linux-mips@linux-mips.org To: David Daney Patchwork: http://patchwork.linux-mips.org/patch/888/ Signed-off-by: Ralf Baechle

MIPS: Fixup of the r4k timer

2010-02-10T21:15:42Z

As reported by Maxime Bizon, the commit "MIPS: PowerTV: Fix support for timer interrupts with > 64 external IRQs" have broken the r4k timer since it didn't initialize the cp0_compare_irq_shift variable used in c0_compare_int_pending() on the architectures whose cpu_has_mips_r2 is false. This patch fixes it via initializing the cp0_compare_irq_shift as the cp0_compare_irq used in the old c0_compare_int_pending(). Reported-by: Maxime Bizon Signed-off-by: Wu Zhangjin Cc: David VomLehn Cc: mbizon@freebox.fr Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/922/ Tested-by: Shane McDonald Signed-off-by: Ralf Baechle

MIPS: PowerTV: Fix support for timer interrupts with > 64 external IRQs

2010-01-27T23:03:31Z

The MIPS processor is limited to 64 external interrupt sources. Using a greater number without IRQ sharing requires reading platform-specific registers. On such platforms, reading the IntCtl register to determine which interrupt corresponds to a timer interrupt will not work. On MIPSR2 systems there is a solution - the TI bit in the Cause register, specifically indicates that a timer interrupt has occured. This patch uses that bit to detect interrupts for MIPSR2 processors, which may be expected to work regardless of how the timer interrupt may be routed in the hardware. Signed-off-by: David VomLehn (dvomlehn@cisco.com) To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/804/ Signed-off-by: Ralf Baechle

MIPS: Cleanup signal code initialization

2009-12-17T01:57:32Z

Signed-off-by: Ralf Baechle Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/709/

MIPS: Modularize COP2 handling

2009-12-17T01:57:30Z

Away with the daemons of ifdef; get ready for future COP2 users. Signed-off-by: Ralf Baechle Patchwork: http://patchwork.linux-mips.org/patch/708/

MIPS: Rewrite sysmips(MIPS_ATOMIC_SET, ...) in C with inline assembler

2009-09-17T18:07:49Z

This way it doesn't have to use CONFIG_CPU_HAS_LLSC anymore. Signed-off-by: Ralf Baechle