<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/arch/mips/kernel/smp-mt.c, branch linux-2.6.28.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-2.6.28.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-2.6.28.y'/>
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<updated>2008-04-28T16:14:26Z</updated>
<entry>
<title>[MIPS] Add support for MIPS CMP platform.</title>
<updated>2008-04-28T16:14:26Z</updated>
<author>
<name>Ralf Baechle</name>
</author>
<published>2008-04-28T16:14:26Z</published>
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<id>urn:sha1:39b8d5254246ac56342b72f812255c8f7a74dca9</id>
<content type='text'>
Signed-off-by: Chris Dearman &lt;chris@mips.com&gt;
Signed-off-by: Atsushi Nemoto &lt;anemo@mba.ocn.ne.jp&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>[MIPS] Remove TLB sanitation code</title>
<updated>2008-04-28T16:14:25Z</updated>
<author>
<name>Chris Dearman</name>
</author>
<published>2007-09-14T20:21:58Z</published>
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<id>urn:sha1:0bfa130e741f8f73a7bbf6a89aad4816e9094a71</id>
<content type='text'>
It is not being used by Malta and shouldn't be needed for MIPSsim.
    
Signed-off-by: Chris Dearman &lt;chris@mips.com&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>[MIPS] SMP: Call platform methods via ops structure.</title>
<updated>2008-01-29T10:14:57Z</updated>
<author>
<name>Ralf Baechle</name>
</author>
<published>2007-11-19T12:23:51Z</published>
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<id>urn:sha1:87353d8ac39c52784da605ecbe965ecdfad609ad</id>
<content type='text'>
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>[MIPS] MT: Scheduler support for SMT</title>
<updated>2008-01-29T10:14:57Z</updated>
<author>
<name>Ralf Baechle</name>
</author>
<published>2007-03-02T20:42:04Z</published>
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<id>urn:sha1:0ab7aefc4d43a6dee26c891b41ef9c7a67d2379b</id>
<content type='text'>
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>[MIPS] Fix "no space between function name and open parenthesis" warnings.</title>
<updated>2007-10-11T22:46:15Z</updated>
<author>
<name>Ralf Baechle</name>
</author>
<published>2007-10-11T22:46:15Z</published>
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<id>urn:sha1:49a89efbbbcc178a39555c43bd59a7593c429664</id>
<content type='text'>
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>[MIPS] SMP: Scatter __cpuinit over the code as needed.</title>
<updated>2007-08-27T01:16:54Z</updated>
<author>
<name>Ralf Baechle</name>
</author>
<published>2007-08-06T13:02:12Z</published>
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<id>urn:sha1:428ab280a0754656fa09304017b0ce626744cc77</id>
<content type='text'>
MIPS doesn't do CPU hotplugging yet but since many of the functions don't
even have an __init let's fix this right.

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>[MIPS] VSMP: Fix initialization ordering bug.</title>
<updated>2007-07-04T14:53:16Z</updated>
<author>
<name>Ralf Baechle</name>
</author>
<published>2007-07-03T16:25:58Z</published>
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<id>urn:sha1:8c976e34516c9e134488babbb95af182340370c8</id>
<content type='text'>
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>[MIPS] Separate performance counter interrupts</title>
<updated>2007-06-14T17:25:15Z</updated>
<author>
<name>Chris Dearman</name>
</author>
<published>2007-05-24T21:24:20Z</published>
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<id>urn:sha1:ffe9ee4709cf513fb80e9b7e04d214dd8b76a10d</id>
<content type='text'>
Support for performance counter overflow interrupt that is on a separate
interrupt from the timer.

Signed-off-by: Chris Dearman &lt;chris@mips.com&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>[MIPS] Define MIPS_CPU_IRQ_BASE in generic header</title>
<updated>2007-02-06T16:53:08Z</updated>
<author>
<name>Atsushi Nemoto</name>
</author>
<published>2007-01-07T17:14:29Z</published>
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<id>urn:sha1:97dcb82de6cc99a5669eb8e342efc24cceb1e77e</id>
<content type='text'>
The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all
platforms and are same value on most platforms (0 or 16, depends on
CONFIG_I8259).  Define them in asm-mips/mach-generic/irq.h and make
them customizable.  This will save a few cycle on each CPU interrupt.

A good side effect is removing some dependencies to MALTA in generic
SMTC code.

Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq
mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing
them might cause some header dependency problem and there seems no
good reason to customize it.  So currently only VR41XX is using custom
MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259.

Testing this patch on those platforms is greatly appreciated.  Thank
you.

Signed-off-by: Atsushi Nemoto &lt;anemo@mba.ocn.ne.jp&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>[MIPS] use generic_handle_irq, handle_level_irq, handle_percpu_irq</title>
<updated>2006-11-30T01:14:46Z</updated>
<author>
<name>Atsushi Nemoto</name>
</author>
<published>2006-11-13T16:13:18Z</published>
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<id>urn:sha1:1417836e81c0ab8f5a0bfeafa90d3eaa41b2a067</id>
<content type='text'>
Further incorporation of generic irq framework.  Replacing __do_IRQ()
by proper flow handler would make the irq handling path a bit simpler
and faster.

* use generic_handle_irq() instead of __do_IRQ().
* use handle_level_irq for obvious level-type irq chips.
* use handle_percpu_irq for irqs marked as IRQ_PER_CPU.
* setup .eoi routine for irq chips possibly used with handle_percpu_irq.

Signed-off-by: Atsushi Nemoto &lt;anemo@mba.ocn.ne.jp&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
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