kernel.git/arch/mips/include/asm/spinlock.h, branch linux-4.1.y

MIPS: End spinlocks with .insn

2017-05-17T19:07:01Z

[ Upstream commit 4b5347a24a0f2d3272032c120664b484478455de ] When building for microMIPS we need to ensure that the assembler always knows that there is code at the target of a branch or jump. Recent toolchains will fail to link a microMIPS kernel when this isn't the case due to what it thinks is a branch to non-microMIPS code. mips-mti-linux-gnu-ld kernel/built-in.o: .spinlock.text+0x2fc: Unsupported branch between ISA modes. mips-mti-linux-gnu-ld final link failed: Bad value This is due to inline assembly labels in spinlock.h not being followed by an instruction mnemonic, either due to a .subsection pseudo-op or the end of the inline asm block. Fix this with a .insn direction after such labels. Signed-off-by: Paul Burton Signed-off-by: James Hogan Reviewed-by: Maciej W. Rozycki Cc: Ralf Baechle Cc: Peter Zijlstra Cc: Ingo Molnar Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Patchwork: https://patchwork.linux-mips.org/patch/15325/ Signed-off-by: James Hogan Signed-off-by: Sasha Levin

MIPS: asm: spinlock: Fix addiu instruction for R10000_LLSC_WAR case

2015-04-10T13:41:46Z

Commit 5753762cbd1c("MIPS: asm: spinlock: Replace "sub" instruction with "addiu") replaced the "sub" instruction with addiu but it did not update the immediate value in the R10000_LLSC_WAR case. Signed-off-by: Markos Chandras Fixes: 5753762cbd1c("MIPS: asm: spinlock: Replace "sub" instruction with "addiu"") Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9385/ Signed-off-by: Ralf Baechle

MIPS: asm: spinlock: Replace "sub" instruction with "addiu"

2015-02-17T15:37:23Z

"sub $reg, imm" is not a real MIPS instruction. The assembler can replace that with "addi $reg, -imm". However, addi has been removed from R6, so we replace the "sub" instruction with the "addiu" one. Signed-off-by: Markos Chandras

MIPS: asm: Rename GCC_OFF12_ASM to GCC_OFF_SMALL_ASM

2015-02-17T15:37:21Z

The GCC_OFF12_ASM macro is used for 12-bit immediate constrains but we will also use it for 9-bit constrains on MIPS R6 so we rename it to something more appropriate. Cc: Maciej W. Rozycki Signed-off-by: Markos Chandras

MIPS: Fix microMIPS LL/SC immediate offsets

2014-11-24T06:45:36Z

In the microMIPS encoding some memory access instructions have their immediate offset reduced to 12 bits only. That does not match the GCC `R' constraint we use in some places to satisfy the requirement, resulting in build failures like this: {standard input}: Assembler messages: {standard input}:720: Error: macro used $at after ".set noat" {standard input}:720: Warning: macro instruction expanded into multiple instructions Fix the problem by defining a macro, `GCC_OFF12_ASM', that expands to the right constraint depending on whether microMIPS or standard MIPS code is produced. Also apply the fix to where `m' is used as in the worst case this change does nothing, e.g. where the pointer was already in a register such as a function argument and no further offset was requested, and in the best case it avoids an extraneous sequence of up to two instructions to load the high 20 bits of the address in the LL/SC loop. This reduces the risk of lock contention that is the higher the more instructions there are in the critical section between LL and SC. Strictly speaking we could just bulk-replace `R' with `ZC' as the latter constraint adjusts automatically depending on the ISA selected. However it was only introduced with GCC 4.9 and we keep supporing older compilers for the standard MIPS configuration, hence the slightly more complicated approach I chose. The choice of a zero-argument function-like rather than an object-like macro was made so that it does not look like a function call taking the C expression used for the constraint as an argument. This is so as not to confuse the reader or formatting checkers like `checkpatch.pl' and follows previous practice. Signed-off-by: Maciej W. Rozycki Signed-off-by: Steven J. Hill Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8482/ Signed-off-by: Ralf Baechle

MIPS: Remove redundant instructions from arch_spin_{,try}lock.

2013-04-26T15:18:24Z

We were doing: SRL $r,$?,16 ANDI $r,$r,0xffff The logical right shift by 16 leaves the upper 16 bits clear, so the subsequent masking out of those bits is redundant, and can safely be removed. Signed-off-by: David Daney Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle

MIPS: Remove further use of .subsection

2013-04-11T13:39:52Z

7837314d141c661c70bc13c5050694413ecfe14a [MIPS: Get rid of branches to .subsections] removed most uses of .subsection] removed most uses of .subsection in inline assembler code. It left the instances in spinlock.h alone because we knew their use was in fairly small files where .subsection use was fine but of course this was a fragile assumption. LTO breaks this assumption resulting in build errors due to exceeded branch range, so remove further instances of .subsection. The two functions that still use .macro don't currently cause issues however this use is still fragile. Signed-off-by: Ralf Baechle

MIPS: Whitespace cleanup.

2013-02-01T09:00:22Z

Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle

MIPS: Microoptimize arch_{read,write}_lock

2011-03-25T17:45:13Z

Signed-off-by: Ralf Baechle

MIPS: Optimize spinlocks.

2010-02-27T11:53:42Z

The current locking mechanism uses a ll/sc sequence to release a spinlock. This is slower than a wmb() followed by a store to unlock. The branching forward to .subsection 2 on sc failure slows down the contended case. So we get rid of that part too. Since we are now working on naturally aligned u16 values, we can get rid of a masking operation as the LHU already does the right thing. The ANDI are reversed for better scheduling on multi-issue CPUs On a 12 CPU 750MHz Octeon cn5750 this patch improves ipv4 UDP packet forwarding rates from 3.58*10^6 PPS to 3.99*10^6 PPS, or about 11%. Signed-off-by: David Daney To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/937/ Signed-off-by: Ralf Baechle