MIPS: Add accessor macros for 64-bit performance counter registers.

2011-10-24T22:34:26Z

Signed-off-by: David Daney To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2789/ Signed-off-by: Ralf Baechle

Fix common misspellings

2011-03-31T14:26:23Z

Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi

MIPS: Add BMIPS CP0 register definitions

2010-10-29T18:08:52Z

Signed-off-by: Kevin Cernekee Cc: mbizon@freebox.fr Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Tested-by: Florian Fainelli Patchwork: https://patchwork.linux-mips.org/patch/1708/ Signed-off-by: Ralf Baechle

MIPS: Define ST0_NMI in asm/mipsregs.h

2010-08-05T12:26:22Z

This is used by the forthcoming OCTEON watchdog patch. Signed-off-by: David Daney To: linux-mips@linux-mips.org To: wim@iguana.be Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1498/ Signed-off-by: Ralf Baechle

MIPS FPU emulator: allow Cause bits of FCSR to be writeable by ctc1

2010-05-15T20:59:53Z

In the FPU emulator code of the MIPS, the Cause bits of the FCSR register are not currently writeable by the ctc1 instruction. In odd corner cases, this can cause problems. For example, a case existed where a divide-by-zero exception was generated by the FPU, and the signal handler attempted to restore the FPU registers to their state before the exception occurred. In this particular setup, writing the old value to the FCSR register would cause another divide-by-zero exception to occur immediately. The solution is to change the ctc1 instruction emulator code to allow the Cause bits of the FCSR register to be writeable. This is the behaviour of the hardware that the code is emulating. This problem was found by Shane McDonald, but the credit for the fix goes to Kevin Kissell. In Kevin's words: I submit that the bug is indeed in that ctc_op: case of the emulator. The Cause bits (17:12) are supposed to be writable by that instruction, but the CTC1 emulation won't let them be updated by the instruction. I think that actually if you just completely removed lines 387-388 [...] things would work a good deal better. At least, it would be a more accurate emulation of the architecturally defined FPU. If I wanted to be really, really pedantic (which I sometimes do), I'd also protect the reserved bits that aren't necessarily writable. Signed-off-by: Shane McDonald To: anemo@mba.ocn.ne.jp To: kevink@paralogos.com To: sshtylyov@mvista.com Patchwork: http://patchwork.linux-mips.org/patch/1205/ Signed-off-by: Ralf Baechle ---

MIPS: Add accessor functions and bit definitions for c0_PageGrain

2010-02-27T11:53:25Z

Signed-off-by: David Daney To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/950/ Signed-off-by: Ralf Baechle

MIPS: Decode c0_config4 for large TLBs.

2010-02-27T11:53:13Z

For processors that have more than 64 TLBs, we need to decode both config1 and config4 to determine the total number TLBs. Signed-off-by: David Daney To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/866/ Signed-off-by: Ralf Baechle

MIPS: PowerTV: Fix support for timer interrupts with > 64 external IRQs

2010-01-27T23:03:31Z

The MIPS processor is limited to 64 external interrupt sources. Using a greater number without IRQ sharing requires reading platform-specific registers. On such platforms, reading the IntCtl register to determine which interrupt corresponds to a timer interrupt will not work. On MIPSR2 systems there is a solution - the TI bit in the Cause register, specifically indicates that a timer interrupt has occured. This patch uses that bit to detect interrupts for MIPSR2 processors, which may be expected to work regardless of how the timer interrupt may be routed in the hardware. Signed-off-by: David VomLehn (dvomlehn@cisco.com) To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/804/ Signed-off-by: Ralf Baechle

MIPS: Add hugetlbfs page defines.

2009-06-17T10:06:30Z

Signed-off-by: David Daney Signed-off-by: Ralf Baechle

MIPS: Fix sign-extension bug in 32-bit kernel on 32-bit hardware.

2009-05-14T12:50:29Z

Probably nobody does arithmetic on cp0 register values so this has never bitten. Signed-off-by: Ralf Baechle

kernel.git/arch/mips/include/asm/mipsregs.h, branch linux-3.2.y