kernel.git/arch/mips/include/asm/cpu.h, branch linux-5.5.y

MIPS: Loongson: Rename LOONGSON1 to LOONGSON32

2019-11-11T18:43:13Z

Now old Loongson-2E/2F use LOONGSON2EF and will be removed in future, newer Loongson-2/3 use LOONGSON64. So rename LOONGSON1 to LOONGSON32 will make the naming style more unified. Signed-off-by: Huacai Chen [paulburton@kernel.org: Fix checkpatch whitespace warning in irqflags.h] Signed-off-by: Paul Burton Cc: Ralf Baechle Cc: James Hogan Cc: linux-mips@linux-mips.org Cc: linux-mips@vger.kernel.org Cc: Fuxin Zhang Cc: Zhangjin Wu Cc: Huacai Chen

MIPS: Loongson64: Rename CPU TYPES

2019-10-31T22:03:10Z

CPU_LOONGSON2 -> CPU_LOONGSON2EF CPU_LOONGSON3 -> CPU_LOONGSON64 As newer loongson-2 products (2G/2H/2K1000) can share kernel implementation with loongson-3 while 2E/2F are less similar with other LOONGSON64 products. Signed-off-by: Jiaxun Yang Signed-off-by: Paul Burton Cc: linux-mips@vger.kernel.org Cc: chenhc@lemote.com Cc: paul.burton@mips.com

MIPS: Loongson: Add Loongson-3A R4 basic support

2019-10-07T16:45:24Z

All Loongson-3 CPU family: Code-name Brand-name PRId Loongson-3A R1 Loongson-3A1000 0x6305 Loongson-3A R2 Loongson-3A2000 0x6308 Loongson-3A R2.1 Loongson-3A2000 0x630c Loongson-3A R3 Loongson-3A3000 0x6309 Loongson-3A R3.1 Loongson-3A3000 0x630d Loongson-3A R4 Loongson-3A4000 0xc000 Loongson-3B R1 Loongson-3B1000 0x6306 Loongson-3B R2 Loongson-3B1500 0x6307 Features of R4 revision of Loongson-3A: - All R2/R3 features, including SFB, V-Cache, FTLB, RIXI, DSP, etc. - Support variable ASID bits. - Support MSA and VZ extensions. - Support CPUCFG (CPU config) and CSR (Control and Status Register) extensions. - 64 entries of VTLB (classic TLB), 2048 entries of FTLB (8-way set-associative). Now 64-bit Loongson processors has three types of PRID.IMP: 0x6300 is the classic one so we call it PRID_IMP_LOONGSON_64C (e.g., Loongson-2E/ 2F/3A1000/3B1000/3B1500/3A2000/3A3000), 0x6100 is for some processors which has reduced capabilities so we call it PRID_IMP_LOONGSON_64R (e.g., Loongson-2K), 0xc000 is supposed to cover all new processors in general (e.g., Loongson-3A4000+) so we call it PRID_IMP_LOONGSON_64G. Signed-off-by: Huacai Chen Signed-off-by: Jiaxun Yang Signed-off-by: Paul Burton Cc: Ralf Baechle Cc: James Hogan Cc: linux-mips@linux-mips.org Cc: linux-mips@vger.kernel.org Cc: Fuxin Zhang Cc: Zhangjin Wu Cc: Huacai Chen

MIPS: Treat Loongson Extensions as ASEs

2019-08-26T10:42:40Z

Recently, binutils had split Loongson-3 Extensions into four ASEs: MMI, CAM, EXT, EXT2. This patch do the samething in kernel and expose them in cpuinfo so applications can probe supported ASEs at runtime. Signed-off-by: Jiaxun Yang Cc: Huacai Chen Cc: Yunqiang Su Cc: stable@vger.kernel.org # v4.14+ Signed-off-by: Paul Burton Cc: linux-mips@vger.kernel.org

MIPS: X1000: Add X1000 system type.

2019-07-30T16:41:14Z

Add X1000 system type for cat /proc/cpuinfo to give out X1000. Signed-off-by: Zhou Yanjie Signed-off-by: Paul Burton Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: ralf@linux-mips.org Cc: paul@crapouillou.net Cc: jhogan@kernel.org Cc: fancer.lancer@gmail.com Cc: chenhc@lemote.com Cc: tglx@linutronix.de Cc: gregkh@linuxfoundation.org Cc: armijn@tjaldur.nl Cc: syq@debian.org Cc: jiaxun.yang@flygoat.com

MIPS: Remove unused R8000 CPU support

2019-07-23T21:33:51Z

Our R8000 CPU support can only be included if a system selects CONFIG_SYS_HAS_CPU_R8000. No system does, making all R8000-related CPU support dead code. Remove it. Signed-off-by: Paul Burton Cc: linux-mips@vger.kernel.org

MIPS: Remove unused R5432 CPU support

2019-07-23T21:33:34Z

Our R5432 CPU support can only be included if a system selects CONFIG_SYS_HAS_CPU_R5432. No system does, making all R5432-related CPU support dead code. Remove it. Signed-off-by: Paul Burton Cc: linux-mips@vger.kernel.org

MIPS: Remove unused R4300 CPU support

2019-07-23T21:33:23Z

Our R4300 CPU support can only be included if a system selects CONFIG_SYS_HAS_CPU_R4300. No system does, making all R4300-related CPU support dead code. Remove it. Signed-off-by: Paul Burton Cc: linux-mips@vger.kernel.org

MIPS: Rename JZRISC to XBURST

2019-07-21T22:23:23Z

The real name of the CPU present in the JZ line of SoCs from Ingenic is XBurst, not JZRISC. Signed-off-by: Paul Cercueil [paul.burton@mips.com: Leave /proc/cpuinfo string as-is.] Signed-off-by: Paul Burton Cc: Ralf Baechle Cc: James Hogan Cc: od@zcrc.me Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org

MIPS: replace MBIT_ULL() with BIT_ULL()

2019-05-29T20:23:09Z

Commit 8bd9cb51daac ("locking/atomics, asm-generic: Move some macros from to a new file") moved BIT_ULL() into . It only includes , so there is no longer "include file recursion hell". Signed-off-by: Masahiro Yamada Signed-off-by: Paul Burton Cc: linux-mips@vger.kernel.org Cc: James Hogan Cc: Huacai Chen Cc: linux-kernel@vger.kernel.org Cc: Ralf Baechle