kernel.git/arch/mips/boot/dts, branch linux-5.16.y

MIPS: ingenic: correct unit node address

2022-04-13T18:03:07Z

[ Upstream commit 8931ddd8d6a55fcefb20f44a38ba42bb746f0b62 ] Unit node addresses should not have leading 0x: Warning (unit_address_format): /nemc@13410000/efuse@d0/eth-mac-addr@0x22: unit name should not have leading "0x" Signed-off-by: Krzysztof Kozlowski Reviewed-by: Paul Cercueil Signed-off-by: Thomas Bogendoerfer Signed-off-by: Sasha Levin

dt-bindings: Rename Ingenic CGU headers to ingenic,*.h

2021-11-12T04:27:14Z

Tidy up a bit the tree, by prefixing all include/dt-bindings/clock/ files related to Ingenic SoCs with 'ingenic,'. Signed-off-by: Paul Cercueil Acked-by: Rob Herring Acked-by: Stephen Boyd Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20211016133322.40771-1-paul@crapouillou.net

Merge tag 'mips_5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

2021-11-05T15:13:19Z

Pull MIPS updates from Thomas Bogendoerfer: - added printing of CPU options for /proc/cpuinfo - removed support for Netlogic SOCs - fixes and cleanup * tag 'mips_5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: MIPS: Cobalt: Explain GT64111 early PCI fixup mips: fix HUGETLB function without THP enabled mips: cm: Convert to bitfield API to fix out-of-bounds access MIPS: Remove NETLOGIC support MIPS: kernel: proc: add CPU option reporting MIPS: kernel: proc: use seq_puts instead of seq_printf MIPS: kernel: proc: fix trivial style errors MIPS: Fix assembly error from MIPSr2 code used within MIPS_ISA_ARCH_LEVEL MIPS: octeon: Remove unused functions MIPS: Loongson64: Add of_node_put() before break bcm47xx: Replace printk(KERN_ALERT ... pci_devname(dev)) with pci_alert() bcm47xx: Get rid of redundant 'else' MIPS: sni: Fix the build MIPS: Avoid macro redefinitions MIPS: loongson64: Fix no screen display during boot-up MIPS: loongson64: make CPU_LOONGSON64 depends on MIPS_FP_SUPPORT

MIPS: Remove NETLOGIC support

2021-10-24T15:24:47Z

No (active) developer owns this hardware, so let's remove Linux support. Signed-off-by: Thomas Bogendoerfer

MIPS: JZ4780: CI20: DTS: add SPI controller config

2021-09-13T01:00:27Z

1. Add nodes for the two SPI controllers found in MIPS Creator CI20. 2. Reparent SPI clock source to effectively use MPLL and set its clock rate to 54MHz. NOTE: To use the SPI controllers, `pinctrl-0` property must be set in order to configure the used pins. As SPI functionality is multiplexed on multiple pin groups, this choice is left to the user. An example configuration: ``` &spi0 { pinctrl-0 = <&pins_spi0>; } pins_spi0: spi0 { function = "ssi0"; groups = "ssi0-dt-e", "ssi0-dr-e", "ssi0-clk-e", "ssi0-ce0-e", "ssi0-ce1-e"; bias-disable; }; ``` Consult the CI20 pinout description for more details. Signed-off-by: Artur Rojek Link: https://lore.kernel.org/r/20210830230139.21476-4-contact@artur-rojek.eu Signed-off-by: Mark Brown

MIPS: mscc: ocelot: mark the phy-mode for internal PHY ports

2021-08-21T08:38:48Z

The ocelot driver was converted to phylink, and that expects a valid phy_interface_t. Without a phy-mode, of_get_phy_mode returns PHY_INTERFACE_MODE_NA, which is not ideal because phylink rejects that. The ocelot driver was patched to treat PHY_INTERFACE_MODE_NA as PHY_INTERFACE_MODE_INTERNAL to work with the broken DT blobs, but we should fix the device trees and specify the phy-mode too. Signed-off-by: Vladimir Oltean Signed-off-by: Thomas Bogendoerfer

MIPS: mscc: ocelot: disable all switch ports by default

2021-08-21T08:38:29Z

The ocelot switch driver used to ignore ports which do not have a phy-handle property and not probe those, but this is not quite ok since it is valid to not have a phy-handle property if there is a fixed-link. It seems that checking for a phy-handle was a proxy for the proper check which is for the status, but that doesn't make a lot of sense, since the ocelot driver already iterates using for_each_available_child_of_node which skips the disabled ports, so I have no idea. Anyway, a widespread pattern in device trees is for a SoC dtsi to disable by default all hardware, and let board dts files enable what is used. So let's do that and enable only the ports with a phy-handle in the pcb120 and pcb123 device tree files. Signed-off-by: Vladimir Oltean Signed-off-by: Thomas Bogendoerfer

MIPS: Retire MACH_PISTACHIO

2021-08-12T14:01:50Z

Now it can be replaced by generic kernel. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer

MIPS: DTS: Pistachio add missing cpc and cdmm

2021-08-12T14:01:49Z

CPC and CDMM addresses are adjustable and we should tell kernel how to place them in devicetree. Note that MACH_PISTACHIO code hardcoded CDMM base to 0x1bdd0000, however it will collide with GIC address range. As we don't have any CDMM device on this platform it won't be a problem. I found another spare range, 0x1bdf0000~0x1be00000 to place CDMM instead. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer

MIPS: generic: Allow generating FIT image for Marduk board

2021-08-12T14:01:49Z

Marduk is based on IMG pistachio SoC. The platform is using MIPS UHI booting protocol and does have a proper devicetree implement, thus it could be a part of generic kernel. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer