<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/arch/mips/boot/dts/mscc, branch linux-5.8.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.8.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.8.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2020-05-13T22:27:19Z</updated>
<entry>
<title>MIPS: dts: mscc: Updated changed name for miim pinctrl function</title>
<updated>2020-05-13T22:27:19Z</updated>
<author>
<name>Lars Povlsen</name>
</author>
<published>2020-05-13T13:23:47Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=d203c2d3eed5a6f1d617591335ccef7b1926461b'/>
<id>urn:sha1:d203c2d3eed5a6f1d617591335ccef7b1926461b</id>
<content type='text'>
This is an add-on patch to the main SoC Sparx5 series
(Message-ID: &lt;20200513125532.24585-1-lars.povlsen@microchip.com&gt;).

This changes the miim pinctrl function name from "miim1" to "miim" due
to refactoring in the driver, obsoleting the instance number.

The change in the driver was to better fit new platforms, as the
instance number is redundant information. Specifically, support for
the Microchip Sparx5 SoC is being submitted, where this change became
necessary.

Reviewed-by: Alexandre Belloni &lt;alexandre.belloni@bootlin.com&gt;
Signed-off-by: Lars Povlsen &lt;lars.povlsen@microchip.com&gt;
Acked-by: Alexandre Belloni &lt;alexandre.belloni@bootlin.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: dts: mscc: describe the PTP ready interrupt</title>
<updated>2019-08-24T14:17:37Z</updated>
<author>
<name>Antoine Tenart</name>
</author>
<published>2019-07-24T08:17:11Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=b4742e6682d5809ddf4d0a63cb57e629e815ec63'/>
<id>urn:sha1:b4742e6682d5809ddf4d0a63cb57e629e815ec63</id>
<content type='text'>
This patch adds a description of the PTP ready interrupt, which can be
triggered when a PTP timestamp is available on an hardware FIFO.

Signed-off-by: Antoine Tenart &lt;antoine.tenart@bootlin.com&gt;
Signed-off-by: Paul Burton &lt;paul.burton@mips.com&gt;
Cc: davem@davemloft.net
Cc: richardcochran@gmail.com
Cc: alexandre.belloni@bootlin.com
Cc: UNGLinuxDriver@microchip.com
Cc: ralf@linux-mips.org
Cc: jhogan@kernel.org
Cc: netdev@vger.kernel.org
Cc: linux-mips@vger.kernel.org
Cc: thomas.petazzoni@bootlin.com
Cc: allan.nielsen@microchip.com
</content>
</entry>
<entry>
<title>MIPS: dts: mscc: describe the PTP register range</title>
<updated>2019-08-24T14:17:33Z</updated>
<author>
<name>Antoine Tenart</name>
</author>
<published>2019-07-24T08:17:09Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=048dc3abe82738567435d9caa106a20eb417b28a'/>
<id>urn:sha1:048dc3abe82738567435d9caa106a20eb417b28a</id>
<content type='text'>
This patch adds one register range within the mscc,vsc7514-switch node,
to describe the PTP registers.

Signed-off-by: Antoine Tenart &lt;antoine.tenart@bootlin.com&gt;
Signed-off-by: Paul Burton &lt;paul.burton@mips.com&gt;
Cc: davem@davemloft.net
Cc: richardcochran@gmail.com
Cc: alexandre.belloni@bootlin.com
Cc: UNGLinuxDriver@microchip.com
Cc: ralf@linux-mips.org
Cc: jhogan@kernel.org
Cc: netdev@vger.kernel.org
Cc: linux-mips@vger.kernel.org
Cc: thomas.petazzoni@bootlin.com
Cc: allan.nielsen@microchip.com
</content>
</entry>
<entry>
<title>net: mscc: ocelot: Add support for tcam</title>
<updated>2019-06-02T20:49:49Z</updated>
<author>
<name>Horatiu Vultur</name>
</author>
<published>2019-05-31T07:16:56Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=b596229448dd2a263cdc4906e60b1b2249777ee4'/>
<id>urn:sha1:b596229448dd2a263cdc4906e60b1b2249777ee4</id>
<content type='text'>
Add ACL support using the TCAM. Using ACL it is possible to create rules
in hardware to filter/redirect frames.

Signed-off-by: Horatiu Vultur &lt;horatiu.vultur@microchip.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>treewide: Add SPDX license identifier - Makefile/Kconfig</title>
<updated>2019-05-21T08:50:46Z</updated>
<author>
<name>Thomas Gleixner</name>
</author>
<published>2019-05-19T12:07:45Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=ec8f24b7faaf3d4799a7c3f4c1b87f6b02778ad1'/>
<id>urn:sha1:ec8f24b7faaf3d4799a7c3f4c1b87f6b02778ad1</id>
<content type='text'>
Add SPDX license identifiers to all Make/Kconfig files which:

 - Have no license information of any form

These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:

  GPL-2.0-only

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'mips_4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux</title>
<updated>2018-10-26T21:43:48Z</updated>
<author>
<name>Linus Torvalds</name>
</author>
<published>2018-10-26T21:43:48Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=cc10ad25bbca3d2925adc32d51cb7a10b837d32c'/>
<id>urn:sha1:cc10ad25bbca3d2925adc32d51cb7a10b837d32c</id>
<content type='text'>
Pull MIPS updates from Paul Burton:

 - kexec support for the generic MIPS platform when running on a CPU
   including the MIPS Coherence Manager &amp; related hardware.

 - Improvements to the definition of memory barriers used around MMIO
   accesses, and fixes in their use.

 - Switch to CONFIG_NO_BOOTMEM from Mike Rapoport, finally dropping
   reliance on the old bootmem code.

 - A number of fixes &amp; improvements for Loongson 3 systems.

 - DT &amp; config updates for the Microsemi Ocelot platform.

 - Workaround to enable USB power on the Netgear WNDR3400v3.

 - Various cleanups &amp; fixes.

* tag 'mips_4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (51 commits)
  MIPS: Cleanup DSP ASE detection
  MIPS: dts: Change upper case to lower case
  MIPS: generic: Add Network, SPI and I2C to ocelot_defconfig
  MIPS: Loongson-3: Fix BRIDGE irq delivery problem
  MIPS: Loongson-3: Fix CPU UART irq delivery problem
  MIPS: Remove unused PREF, PREFE &amp; PREFX macros
  MIPS: lib: Use kernel_pref &amp; user_pref in memcpy()
  MIPS: Remove unused CAT macro
  MIPS: Add kernel_pref &amp; user_pref helpers
  MIPS: Remove unused TTABLE macro
  MIPS: Remove unused PIC macros
  MIPS: Remove unused MOVN &amp; MOVZ macros
  MIPS: Provide actually relaxed MMIO accessors
  MIPS: Enforce strong ordering for MMIO accessors
  MIPS: Correct `mmiowb' barrier for `wbflush' platforms
  MIPS: Define MMIO ordering barriers
  MIPS: mscc: add PCB120 to the ocelot fitImage
  MIPS: mscc: add DT for Ocelot PCB120
  MIPS: memset: Limit excessive `noreorder' assembly mode use
  MIPS: memset: Fix CPU_DADDI_WORKAROUNDS `small_fixup' regression
  ...
</content>
</entry>
<entry>
<title>MIPS: mscc: add DT for Ocelot PCB120</title>
<updated>2018-10-09T17:37:27Z</updated>
<author>
<name>Quentin Schulz</name>
</author>
<published>2018-10-08T10:14:44Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=116edf6e5239ee834ae4a8c122f319a298ef052b'/>
<id>urn:sha1:116edf6e5239ee834ae4a8c122f319a298ef052b</id>
<content type='text'>
The Ocelot PCB120 evaluation board is different from the PCB123 in that
it has 4 external VSC8584 (or VSC8574) PHYs.

It uses the SoC's second MDIO bus for external PHYs which have a
reversed address on the bus (i.e. PHY4 is on address 3, PHY5 is on
address 2, PHY6 on 1 and PHY7 on 0).

Here is how the PHYs are connected to the switch ports:
port 0: phy0 (internal)
port 1: phy1 (internal)
port 2: phy2 (internal)
port 3: phy3 (internal)
port 4: phy7
port 5: phy4
port 6: phy6
port 9: phy5

Reviewed-by: Alexandre Belloni &lt;alexandre.belloni@bootlin.com&gt;
Signed-off-by: Quentin Schulz &lt;quentin.schulz@bootlin.com&gt;
Signed-off-by: Paul Burton &lt;paul.burton@mips.com&gt;
Patchwork: https://patchwork.linux-mips.org/patch/20869/
Cc: ralf@linux-mips.org
Cc: jhogan@kernel.org
Cc: robh+dt@kernel.org
Cc: mark.rutland@arm.com
Cc: davem@davemloft.net
Cc: andrew@lunn.ch
Cc: f.fainelli@gmail.com
Cc: allan.nielsen@microchip.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: netdev@vger.kernel.org
Cc: thomas.petazzoni@bootlin.com
Cc: antoine.tenart@bootlin.com
</content>
</entry>
<entry>
<title>MIPS: mscc: ocelot: add SerDes mux DT node</title>
<updated>2018-10-05T21:36:44Z</updated>
<author>
<name>Quentin Schulz</name>
</author>
<published>2018-10-04T12:22:05Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=1d6a632c4754fd070f5390e284e74796c3ef0149'/>
<id>urn:sha1:1d6a632c4754fd070f5390e284e74796c3ef0149</id>
<content type='text'>
The Microsemi Ocelot has a set of register for SerDes/switch port muxing
as well as PCIe muxing for a specific SerDes, so let's add the device
and all SerDes in the Device Tree.

Reviewed-by: Florian Fainelli &lt;f.fainelli@gmail.com&gt;
Acked-by: Paul Burton &lt;paul.burton@mips.com&gt;
Signed-off-by: Quentin Schulz &lt;quentin.schulz@bootlin.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>MIPS: mscc: ocelot: make HSIO registers address range a syscon</title>
<updated>2018-10-05T21:36:43Z</updated>
<author>
<name>Quentin Schulz</name>
</author>
<published>2018-10-04T12:21:58Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=3df0e6804f0e36e347882789fcaf70cdac890707'/>
<id>urn:sha1:3df0e6804f0e36e347882789fcaf70cdac890707</id>
<content type='text'>
HSIO contains registers for PLL5 configuration, SerDes/switch port
muxing and a thermal sensor, hence we can't keep it in the switch DT
node.

Acked-by: Paul Burton &lt;paul.burton@mips.com&gt;
Acked-by: Alexandre Belloni &lt;alexandre.belloni@bootlin.com&gt;
Signed-off-by: Quentin Schulz &lt;quentin.schulz@bootlin.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>MIPS: dts: mscc: enable i2c on ocelot_pcb123</title>
<updated>2018-09-05T23:05:58Z</updated>
<author>
<name>Alexandre Belloni</name>
</author>
<published>2018-08-31T15:11:14Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=7c45885ea92972e7909847c39bd1698b76dffd73'/>
<id>urn:sha1:7c45885ea92972e7909847c39bd1698b76dffd73</id>
<content type='text'>
Enable the i2c controller on ocelot PCB123. While there are no i2c devices
on the board itself, it can be used to control the SFP transceivers.

Signed-off-by: Alexandre Belloni &lt;alexandre.belloni@bootlin.com&gt;
Signed-off-by: Paul Burton &lt;paul.burton@mips.com&gt;
Patchwork: https://patchwork.linux-mips.org/patch/20352/
Cc: Wolfram Sang &lt;wsa@the-dreams.de&gt;
Cc: Jarkko Nikula &lt;jarkko.nikula@linux.intel.com&gt;
Cc: James Hogan &lt;jhogan@kernel.org&gt;
Cc: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Cc: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Cc: linux-i2c@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: Thomas Petazzoni &lt;thomas.petazzoni@bootlin.com&gt;
Cc: Allan Nielsen &lt;allan.nielsen@microchip.com&gt;
</content>
</entry>
</feed>
