kernel.git/arch/mips/boot/dts/mscc, branch linux-5.13.y

MIPS: mscc: Add serval support

2020-11-12T22:35:15Z

Add a device trees and FIT image support for the Microsemi Serval SoC which belongs to same family of the Ocelot SoC. It is based on the work of Lars Povlsen . Signed-off-by: Gregory CLEMENT Acked-by: Alexandre Belloni Signed-off-by: Thomas Bogendoerfer

MIPS: mscc: Add jaguar2 support

2020-11-12T22:34:25Z

Add a device trees and FIT image support for the Microsemi Jaguar2 SoC which belongs to same family of the Ocelot SoC. It is based on the work of Lars Povlsen . Signed-off-by: Gregory CLEMENT Acked-by: Alexandre Belloni Signed-off-by: Thomas Bogendoerfer

MIPS: mscc: Add luton PC0B91 device tree

2020-11-12T22:33:42Z

Add a device tree for the Microsemi Luton PCB091 evaluation board. It is based on the work of Lars Povlsen . Signed-off-by: Gregory CLEMENT Acked-by: Alexandre Belloni Signed-off-by: Thomas Bogendoerfer

MIPS: mscc: Add luton dtsi

2020-11-12T22:32:39Z

Add a device tree include file for the Microsemi Luton SoC which belongs to same family of the Ocelot SoC. It is based on the work of Lars Povlsen . Signed-off-by: Gregory CLEMENT Acked-by: Alexandre Belloni Signed-off-by: Thomas Bogendoerfer

MIPS: mscc: Prepare configuration to handle more SoCs

2020-11-12T22:31:47Z

Ocelot belongs to a family of SoC named the VCore III. In order to add these new Soc, use the new symbol SOC_VCOREIII instead of a one dedicated to Ocelot. In order to avoid regression on driver building, the MSCC_OCELOT configuration symbol is kept until the driver will be converted. Signed-off-by: Gregory CLEMENT Acked-by: Alexandre Belloni Signed-off-by: Thomas Bogendoerfer

net: mscc: ocelot: add definitions for VCAP ES0 keys, actions and target

2020-09-30T01:26:12Z

As a preparation step for the offloading to ES0, let's create the infrastructure for talking with this hardware block. Signed-off-by: Vladimir Oltean Signed-off-by: David S. Miller

net: mscc: ocelot: add definitions for VCAP IS1 keys, actions and target

2020-09-30T01:26:12Z

As a preparation step for the offloading to IS1, let's create the infrastructure for talking with this hardware block. Signed-off-by: Vladimir Oltean Signed-off-by: David S. Miller

MIPS: dts: ocelot: describe the load/save GPIO

2020-06-24T21:33:16Z

This patch adds a description of the load/save GPIN pin, used in the VSC8584 PHY for timestamping operations. The related pinctrl description is also added. Signed-off-by: Quentin Schulz Signed-off-by: Antoine Tenart Signed-off-by: David S. Miller

MIPS: dts: mscc: Updated changed name for miim pinctrl function

2020-05-13T22:27:19Z

This is an add-on patch to the main SoC Sparx5 series (Message-ID: <20200513125532.24585-1-lars.povlsen@microchip.com>). This changes the miim pinctrl function name from "miim1" to "miim" due to refactoring in the driver, obsoleting the instance number. The change in the driver was to better fit new platforms, as the instance number is redundant information. Specifically, support for the Microchip Sparx5 SoC is being submitted, where this change became necessary. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen Acked-by: Alexandre Belloni Signed-off-by: Thomas Bogendoerfer

MIPS: dts: mscc: describe the PTP ready interrupt

2019-08-24T14:17:37Z

This patch adds a description of the PTP ready interrupt, which can be triggered when a PTP timestamp is available on an hardware FIFO. Signed-off-by: Antoine Tenart Signed-off-by: Paul Burton Cc: davem@davemloft.net Cc: richardcochran@gmail.com Cc: alexandre.belloni@bootlin.com Cc: UNGLinuxDriver@microchip.com Cc: ralf@linux-mips.org Cc: jhogan@kernel.org Cc: netdev@vger.kernel.org Cc: linux-mips@vger.kernel.org Cc: thomas.petazzoni@bootlin.com Cc: allan.nielsen@microchip.com