<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/arch/mips/bcm63xx/cpu.c, branch linux-3.10.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-3.10.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-3.10.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2013-05-07T23:19:03Z</updated>
<entry>
<title>MIPS: BCM63XX: add basic BCM6362 support</title>
<updated>2013-05-07T23:19:03Z</updated>
<author>
<name>Jonas Gorski</name>
</author>
<published>2013-03-21T14:03:17Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=2c8aaf71b0a4738ae8cb70d9367089bdb892aea3'/>
<id>urn:sha1:2c8aaf71b0a4738ae8cb70d9367089bdb892aea3</id>
<content type='text'>
Add basic support for detecting and booting the BCM6362.

Signed-off-by: Jonas Gorski &lt;jogo@openwrt.org&gt;
Patchwork: http://patchwork.linux-mips.org/patch/5009/
Acked-by: John Crispin &lt;blogic@openwrt.org&gt;
</content>
</entry>
<entry>
<title>MIPS: BCM63XX: rework chip detection</title>
<updated>2013-05-07T23:19:03Z</updated>
<author>
<name>Jonas Gorski</name>
</author>
<published>2013-03-21T14:03:16Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=13be798c57ebe5df09254832330f48c936ac39fd'/>
<id>urn:sha1:13be798c57ebe5df09254832330f48c936ac39fd</id>
<content type='text'>
Instead of trying to use a correlation of cpu prid and chip id and
hoping they will always be unique, use the cpu prid to determine the
chip id register location and just read out the chip id.

Signed-off-by: Jonas Gorski &lt;jogo@openwrt.org&gt;
Patchwork: http://patchwork.linux-mips.org/patch/5008/
Acked-by: John Crispin &lt;blogic@openwrt.org&gt;
</content>
</entry>
<entry>
<title>MIPS: BCM63XX: fix revision ID width</title>
<updated>2013-05-07T23:19:03Z</updated>
<author>
<name>Jonas Gorski</name>
</author>
<published>2013-03-21T14:03:15Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=6605428c506bea269ca6c4aed85e97fbee2cbe7b'/>
<id>urn:sha1:6605428c506bea269ca6c4aed85e97fbee2cbe7b</id>
<content type='text'>
The REVID is only 8 bit wide.

Signed-off-by: Jonas Gorski &lt;jogo@openwrt.org&gt;
Patchwork: http://patchwork.linux-mips.org/patch/5007/
Acked-by: John Crispin &lt;blogic@openwrt.org&gt;
</content>
</entry>
<entry>
<title>MIPS: BCM63XX: Add basic BCM6328 support</title>
<updated>2012-07-24T14:33:12Z</updated>
<author>
<name>Jonas Gorski</name>
</author>
<published>2012-07-24T14:33:12Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=e5766aea5b9b7519654261c27b639f567b5415b4'/>
<id>urn:sha1:e5766aea5b9b7519654261c27b639f567b5415b4</id>
<content type='text'>
This includes CPU speed, memory size detection and working UART, but
lacking the appropriate drivers, no support for attached flash.

Signed-off-by: Jonas Gorski &lt;jonas.gorski@gmail.com&gt;
Cc: linux-mips@linux-mips.org
Cc: Maxime Bizon &lt;mbizon@freebox.fr&gt;
Cc: Florian Fainelli &lt;florian@openwrt.org&gt;
Cc: Kevin Cernekee &lt;cernekee@gmail.com&gt;
Patchwork: https://patchwork.linux-mips.org/patch/3951/
Reviewed-by: Florian Fainelli &lt;florian@openwrt.org&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: BCM63XX: Use the Chip ID register for identifying the SoC</title>
<updated>2012-07-24T14:33:12Z</updated>
<author>
<name>Jonas Gorski</name>
</author>
<published>2012-07-24T14:33:12Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=288752a8aa1be6cf89ee5066435a617efd97fb86'/>
<id>urn:sha1:288752a8aa1be6cf89ee5066435a617efd97fb86</id>
<content type='text'>
Newer BCM63XX SoCs use virtually the same CPU ID, differing only in the
revision bits. But since they all have the Chip ID register at the same
location, we can use that to identify the SoC we are running on.

Signed-off-by: Jonas Gorski &lt;jonas.gorski@gmail.com&gt;
Cc: linux-mips@linux-mips.org
Cc: Maxime Bizon &lt;mbizon@freebox.fr&gt;
Cc: Florian Fainelli &lt;florian@openwrt.org&gt;
Cc: Kevin Cernekee &lt;cernekee@gmail.com&gt;
Patchwork: https://patchwork.linux-mips.org/patch/3955/
Reviewed-by: Florian Fainelli &lt;florian@openwrt.org&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: BCM63xx: Fix SDRAM size computation for BCM6345</title>
<updated>2011-12-07T22:03:04Z</updated>
<author>
<name>Florian Fainelli</name>
</author>
<published>2011-11-16T19:10:36Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=d61fcfe2bbb27d4da18c609cf279627ae1b74151'/>
<id>urn:sha1:d61fcfe2bbb27d4da18c609cf279627ae1b74151</id>
<content type='text'>
Instead of hardcoding the amount of available RAM, read the number of
effective multiples of 8MB from SDRAM_MBASE_REG.

Signed-off-by: Florian Fainelli &lt;florian@openwrt.org&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3008/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: BCM63XX: Add support for bcm6368 CPU.</title>
<updated>2011-12-07T22:03:04Z</updated>
<author>
<name>Maxime Bizon</name>
</author>
<published>2011-11-04T18:09:35Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=04712f3ff6e3a42ef658b55b0f99478f4f0682e3'/>
<id>urn:sha1:04712f3ff6e3a42ef658b55b0f99478f4f0682e3</id>
<content type='text'>
Signed-off-by: Maxime Bizon &lt;mbizon@freebox.fr&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2892/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: BCM63XX: Cleanup cpu registers.</title>
<updated>2011-12-07T22:03:03Z</updated>
<author>
<name>Maxime Bizon</name>
</author>
<published>2011-11-04T18:09:29Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=ec68c5206ab32f67583c1297f7883ceb91b043eb'/>
<id>urn:sha1:ec68c5206ab32f67583c1297f7883ceb91b043eb</id>
<content type='text'>
Use preprocessor when possible to avoid duplicated and error-prone
code.

Signed-off-by: Maxime Bizon &lt;mbizon@freebox.fr&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2897/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Decouple BMIPS CPU support from bcm47xx/bcm63xx SoC code</title>
<updated>2010-10-29T18:08:50Z</updated>
<author>
<name>Kevin Cernekee</name>
</author>
<published>2010-10-16T21:22:30Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=602977b0d672687909b0cb0542ede134ed6ef858'/>
<id>urn:sha1:602977b0d672687909b0cb0542ede134ed6ef858</id>
<content type='text'>
BMIPS processor cores are used in 50+ different chipsets spread across
5+ product lines.  In many cases the chipsets do not share the same
peripheral register layouts, the same register blocks, the same
interrupt controllers, the same memory maps, or much of anything else.

But, across radically different SoCs that share nothing more than the
same BMIPS CPU, a few things are still mostly constant:

SMP operations
Access to performance counters
DMA cache coherency quirks
Cache and memory bus configuration

So, it makes sense to treat each BMIPS processor type as a generic
"building block," rather than tying it to a specific SoC.  This makes it
easier to support a large number of BMIPS-based chipsets without
unnecessary duplication of code, and provides the infrastructure needed
to support BMIPS-proprietary features.

Signed-off-by: Kevin Cernekee &lt;cernekee@gmail.com&gt;
Cc: mbizon@freebox.fr
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Tested-by: Florian Fainelli &lt;ffainelli@freebox.fr&gt;
Patchwork: https://patchwork.linux-mips.org/patch/1706/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org
</content>
</entry>
<entry>
<title>MIPS: BCM63xx: Add support for second uart.</title>
<updated>2010-04-12T16:26:18Z</updated>
<author>
<name>Maxime Bizon</name>
</author>
<published>2010-01-30T17:34:55Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=524ef29cff593ab6635cda2a17b331bede58a396'/>
<id>urn:sha1:524ef29cff593ab6635cda2a17b331bede58a396</id>
<content type='text'>
The BCm63xx SOC has two uarts.  Some boards use the second one for
bluetooth.  This patch changes platform device registration code to
handle this.  Changes to the UART driver were already merged in
6a2c7eabfd09ca7986bf96b8958a87ca041a19d8.

Signed-off-by: Maxime Bizon &lt;mbizon@freebox.fr&gt;
To: linux-mips@linux-mips.org
Cc: Maxime Bizon &lt;mbizon@freebox.fr&gt;
Patchwork: http://patchwork.linux-mips.org/patch/900/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
</feed>
