kernel.git/arch/mips/ath79/clock.c, branch linux-4.10.y

MIPS: ath79: Fix test for error return of clk_register_fixed_factor().

2016-09-13T12:13:26Z

clk_register_fixed_factor returns an ERR_PTR in case of an error and should have an IS_ERR check instead of a null check. The Coccinelle semantic patch used to find this issue is as follows: @@ expression e; statement S; @@ *e = clk_register_fixed_factor(...); if (!e) S Signed-off-by: Amitoj Kaur Chawla Cc: julia.lawall@lip6.fr Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13894/ Signed-off-by: Ralf Baechle

MIPS: ath79: Remove CLK_IS_ROOT

2016-05-13T13:30:25Z

This flag is a no-op now (see commit 47b0eeb3dc8a "clk: Deprecate CLK_IS_ROOT", 2016-02-02) so remove it. Signed-off-by: Stephen Boyd Cc: Antony Pavlov Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13133/ Signed-off-by: Ralf Baechle

MIPS: ath79: update devicetree clock support for AR9331

2016-05-13T12:01:46Z

Signed-off-by: Antony Pavlov Cc: Gabor Juhos Cc: Alban Bedel Cc: Michael Turquette Cc: Stephen Boyd Cc: Rob Herring Cc: linux-clk@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12879/ Signed-off-by: Ralf Baechle

MIPS: ath79: update devicetree clock support for AR9132

2016-05-13T12:01:45Z

Current ath79 clock.c code does not read reference clock and pll setup from devicetree. E.g. you can set any clock rate value in board DTS but it will have no effect on the real clk calculation. This patch fixes some AR9132 devicetree clock support defects: * clk initialization function ath79_clocks_init_dt_ng() is introduced; it actually gets pll block base register address and reference clock from devicetree; * pll register parsing code is moved to the separate ar724x_clk_init() function; this function can be called from platform code or from devicetree code. Also mips_hpt_frequency value is set from dt, so the appropriate clock parameter is added to the cpu@0 devicetree node. The same approach can be used for adding AR9331 devicetree support. Signed-off-by: Antony Pavlov Cc: Gabor Juhos Cc: Alban Bedel Cc: Michael Turquette Cc: Stephen Boyd Cc: Rob Herring Cc: linux-clk@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12876/ Signed-off-by: Ralf Baechle

MIPS: ath79: Introduce

2016-05-13T12:01:45Z

The include/dt-bindings/clock/ath79-clk.h header file is introduced so we can use symbolic identifiers for SoC clocks. Signed-off-by: Antony Pavlov Cc: Gabor Juhos Cc: Alban Bedel Cc: Michael Turquette Cc: Stephen Boyd Cc: Rob Herring Cc: linux-mips@linux-mips.org Cc: linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12875/ Signed-off-by: Ralf Baechle

MIPS: ath79: Fix the ar913x reference clock rate

2016-04-03T10:32:10Z

The reference clock on ar913x is at 40MHz and not 5MHz. The current implementation use the wrong reference rate because it doesn't take the PLL divider in account. But if we fix the code to use the divider it becomes identical with the implementation for ar724x, so just drop the broken ar913x implementation. Signed-off-by: Alban Bedel Tested-by: Antony Pavlov Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12871/ Signed-off-by: Ralf Baechle

MIPS: ath79: Fix the ar724x clock calculation

2016-04-03T10:32:09Z

According to the AR7242 datasheet section 2.8, AR724X CPUs use a 40MHz input clock as the REF_CLK instead of 5MHz. The correct CPU PLL calculation procedure is as follows: CPU_PLL = (FB * REF_CLK) / REF_DIV / 2. This patch is compatible with the current calculation procedure with default FB and REF_DIV values. Tested on AR7240, AR7241 and AR7242. Signed-off-by: Weijie Gao Signed-off-by: Alban Bedel (Fixed the commit log message) Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12870/ Signed-off-by: Ralf Baechle

MIPS: ath79: Add OF support to the clocks

2015-06-21T19:54:06Z

Allow using the SoC clocks in the device tree. Signed-off-by: Alban Bedel Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle

MIPS: ath79: Use the common clk API

2015-06-21T19:53:51Z

Make the code simpler and open the way for device tree clocks. [ralf@linux-mips.org: Resolved conflict with 2a552da6 (MIPS/IRQCHIP: Move irq_chip from arch/mips to drivers/irqchip.)] Signed-off-by: Alban Bedel Cc: linux-mips@linux-mips.org Cc: Andrew Bresticker Cc: Qais Yousef Cc: Wolfram Sang Cc: Sergey Ryazanov Cc: Gabor Juhos Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9774/ Signed-off-by: Ralf Baechle

MIPS: ath79: Correctly name the defines for the PLL_FB register

2015-06-21T19:53:49Z

This register is named PLL_FB and is not a divider but a multiplier. To make things less confusing rename the ARxxxx_PLL_DIV_SHIFT and ARxxxx_PLL_DIV_MASK macros to ARxxxx_PLL_FB_SHIFT and ARxxxx_PLL_FB_MASK. Signed-off-by: Alban Bedel Cc: linux-mips@linux-mips.org Cc: Andrew Bresticker Cc: Qais Yousef Cc: Wolfram Sang Cc: Sergey Ryazanov Cc: Gabor Juhos Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9772/ Signed-off-by: Ralf Baechle