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<title>kernel.git/arch/mips/alchemy/common/clock.c, branch linux-3.18.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-3.18.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-3.18.y'/>
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<updated>2015-03-06T22:52:54Z</updated>
<entry>
<title>MIPS: Alchemy: Fix cpu clock calculation</title>
<updated>2015-03-06T22:52:54Z</updated>
<author>
<name>Manuel Lauss</name>
</author>
<published>2015-02-18T10:01:56Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=6a5f2ac063bce807cff8fb1e575a9fca280579a5'/>
<id>urn:sha1:6a5f2ac063bce807cff8fb1e575a9fca280579a5</id>
<content type='text'>
commit 69e4e63ec816a7e22cc3aa14bc7ef4ac734d370c upstream.

The current code uses bits 0-6 of the sys_cpupll register to calculate
core clock speed.  However this is only valid on Au1300, on all earlier
models the hardware only uses bits 0-5 to generate core clock.

This fixes clock calculation on the MTX1 (Au1500), where bit 6 of cpupll
is set as well, which ultimately lead the code to calculate a bogus cpu
core clock and also uart base clock down the line.

Signed-off-by: Manuel Lauss &lt;manuel.lauss@gmail.com&gt;
Reported-by: John Crispin &lt;blogic@openwrt.org&gt;
Tested-by: Bruno Randolf &lt;br1@einfach.org&gt;
Cc: Linux-MIPS &lt;linux-mips@linux-mips.org&gt;
Patchwork: https://patchwork.linux-mips.org/patch/9279/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>MIPS: Alchemy: remove old clock support</title>
<updated>2014-07-30T12:12:00Z</updated>
<author>
<name>Manuel Lauss</name>
</author>
<published>2014-07-23T14:36:57Z</published>
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<id>urn:sha1:72e1e2a30f67fc19a958be6c1818e7e6cb1573fe</id>
<content type='text'>
With the clock framework in place, remove unused functions and bits,
and drop the CLK_IGNORE_UNUSED flag, which is now unneeded.

Signed-off-by: Manuel Lauss &lt;manuel.lauss@gmail.com&gt;
Cc: Linux-MIPS &lt;linux-mips@linux-mips.org&gt;
Patchwork: https://patchwork.linux-mips.org/patch/7473/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Alchemy: clock framework integration of onchip clocks</title>
<updated>2014-07-30T12:08:42Z</updated>
<author>
<name>Manuel Lauss</name>
</author>
<published>2014-07-23T14:36:48Z</published>
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<id>urn:sha1:474402291a0ad4778a4e5fdff6ae507b2a26d809</id>
<content type='text'>
This patch introduces common clock framework integration for all
configurable on-chip clocks on Alchemy chips:

- 2 or 3 PLLs which generate integer multiples of the root rate 12MHz,
- 6 dividers which take one of the 3 PLLs as input and divide their
  rate by either multiples of 2 or 1 (Au1300).
- another bank of up to 6 muxes which take either one of the 6
  above dividers or one of the PLLs directly and divide their rate
  further by 1, 2, 3 or 4.
- a few other sources which are used by onchip peripherals and are
  informational.

This implementation will take the clock tree as it was set up
by boot firmware: all in-kernel boards should continue to work
without having to set up the clock tree in board code.

CLK_IGNORE_DISABLED will be removed once all drivers have been
converted.

Signed-off-by: Manuel Lauss &lt;manuel.lauss@gmail.com&gt;
Cc: Mike Turquette &lt;mturquette@linaro.org&gt;
Cc: Linux-MIPS &lt;linux-mips@linux-mips.org&gt;
Patchwork: https://patchwork.linux-mips.org/patch/7466/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
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