kernel.git/arch/microblaze/kernel, branch linux-2.6.34.y

microblaze: Fix module loading on system with WB cache

2010-05-14T05:43:38Z

There is necessary to flush whole dcache. Icache work should be done in kernel/module.c. Signed-off-by: Michal Simek

microblaze: export assembly functions used by modules

2010-05-13T10:11:42Z

Export __strncpy_user, memory_size, ioremap_bot for modules. Signed-off-by: Michal Simek

microblaze: Remove compilation warnings in cache macro

2010-05-13T08:55:47Z

CC arch/microblaze/kernel/cpu/cache.o arch/microblaze/kernel/cpu/cache.c: In function '__invalidate_dcache_range_wb': arch/microblaze/kernel/cpu/cache.c:398: warning: ISO C90 forbids mixed declarations and code arch/microblaze/kernel/cpu/cache.c: In function '__flush_dcache_range_wb': arch/microblaze/kernel/cpu/cache.c:509: warning: ISO C90 forbids mixed declara Signed-off-by: Michal Simek

microblaze: export assembly functions used by modules

2010-05-13T08:46:04Z

Modules that use copy_{to,from}_user(), memcpy(), and memset() fail to build in certain circumstances. Signed-off-by: Steven J. Magnani Signed-off-by: Michal Simek

microblaze: re-enable interrupts before calling schedule

2010-05-13T07:21:01Z

schedule() should not be called with interrupts disabled. Signed-off-by: Steven J. Magnani Signed-off-by: Michal Simek

microblaze: Optimize CACHE_LOOP_LIMITS and CACHE_RANGE_LOOP macros

2010-05-06T09:22:00Z

1. Remove CACHE_ALL_LOOP2 macro because it is identical to CACHE_ALL_LOOP 2. Change BUG_ON to WARN_ON 3. Remove end aligned from CACHE_LOOP_LIMITS. C implementation do not need aligned end address and ASM code do aligned in their macros 4. ASM optimized CACHE_RANGE_LOOP_1/2 macros needs to get aligned end address. Because end address is compound from start + size, end address is the first address which is exclude. Here is the corresponding code which describe it. + int align = ~(line_length - 1); + end = ((end & align) == end) ? end - line_length : end & align; a) end is aligned: it is necessary to subtruct line length because we don't want to work with next cacheline b) end address is not aligned: Just align it to be ready for ASM code. Signed-off-by: Michal Simek

microblaze: cpuinfo shows cache line length

2010-05-06T09:21:59Z

Show cache line length in /proc/cpuinfo. Signed-off-by: Michal Simek

microblaze: Fix typo fault in cache code

2010-05-06T09:21:59Z

Copy & paste error. Signed-off-by: Michal Simek

microblaze: Fix consistent code

2010-05-06T09:21:59Z

This patch fix consistent code which had problems with consistent_free function. I am not sure if we need to call flush_tlb_all after it but it keeps tlbs synced. I added noMMU and MMU version together. Uncached shadow feature is not tested. Signed-off-by: Michal Simek

microblaze: Remove "cache" optimized copy_page function

2010-05-06T09:21:58Z

Current implementation doesn't handle dcache_line_length correctly that's why is better to use generic memcpy. Cache optimized function could be good way howto improve performance but must be based on benchmarking not blind function like this. Signed-off-by: Michal Simek