kernel.git/arch/i386/kernel/cpu, branch linux-2.6.19.y

[PATCH] thermal throttle: sysfs error checking

2006-10-13T15:35:39Z

Get rid of warning in the thermal throttling code about not checking sysfs return values. Signed-off-by: Stephen Hemminger Signed-off-by: Linus Torvalds

BUG_ON cleanups in arch/i386

2006-10-03T21:34:58Z

This changes a couple of if() BUG(); constructs to BUG_ON(); so it can be safely optimized away. Signed-off-by: Eric Sesterhenn Signed-off-by: Adrian Bunk

x86: Fix booting with "no387 nofxsr"

2006-10-03T16:47:14Z

Jesper Juhl reported that testing the software math-emulation by forcing "no387" doesn't work on modern CPU's. The reason was two-fold: - you also need to pass in "nofxsr" to make sure that we not only don't touch the old i387 legacy hardware, it also needs to disable the modern XMM/FXSR sequences - "nofxsr" didn't actually clear the capability bits immediately, leaving the early boot sequence still using FXSR until we got to the identify_cpu() stage. This fixes the "nofxsr" flag to take effect immediately on the boot CPU. Debugging by Randy Dunlap Acked-by: Randy Dunlap Cc: Jesper Juhl Cc: Andi Kleen Signed-off-by: Linus Torvalds

[CPUFREQ] Make acpi-cpufreq unsticky again.

2006-10-01T03:19:38Z

This caused suspend/resume regressions. Signed-off-by: Dave Jones

[CPUFREQ] longhaul: remove duplicated code.

2006-09-27T21:03:36Z

removing duplicated code. Signed-off-by: Rafa� Bilski Signed-off-by: Dave Jones

[CPUFREQ] Longhaul - Disable arbiter CLE266

2006-09-27T03:12:02Z

Please ignore previous message. This patch is adding support for CPU connected to CLE266 chipset. For older CPU this is only way. For "Powersaver" processor this way will be used if ACPI C3 isn't supported. I have tested it. It seems to work exacly like ACPI. But it is less safe. On CLE266 chipset port 0x22 is blocking processor access to PCI bus too. Signed-off-by: Rafa³ Bilski Signed-off-by: Dave Jones

[CPUFREQ] Fix section mismatch warning

2006-09-27T03:02:45Z

Make the sections proper and get rid of section mismatch warnings. Signed-off-by: Venkatesh Pallipadi Signed-off-by: Dave Jones

Merge branch 'for-linus' of git://one.firstfloor.org/home/andi/git/linux-2.6

2006-09-26T20:07:55Z

* 'for-linus' of git://one.firstfloor.org/home/andi/git/linux-2.6: (225 commits) [PATCH] Don't set calgary iommu as default y [PATCH] i386/x86-64: New Intel feature flags [PATCH] x86: Add a cumulative thermal throttle event counter. [PATCH] i386: Make the jiffies compares use the 64bit safe macros. [PATCH] x86: Refactor thermal throttle processing [PATCH] Add 64bit jiffies compares (for use with get_jiffies_64) [PATCH] Fix unwinder warning in traps.c [PATCH] x86: Allow disabling early pci scans with pci=noearly or disallowing conf1 [PATCH] x86: Move direct PCI scanning functions out of line [PATCH] i386/x86-64: Make all early PCI scans dependent on CONFIG_PCI [PATCH] Don't leak NT bit into next task [PATCH] i386/x86-64: Work around gcc bug with noreturn functions in unwinder [PATCH] Fix some broken white space in ia32_signal.c [PATCH] Initialize argument registers for 32bit signal handlers. [PATCH] Remove all traces of signal number conversion [PATCH] Don't synchronize time reading on single core AMD systems [PATCH] Remove outdated comment in x86-64 mmconfig code [PATCH] Use string instructions for Core2 copy/clear [PATCH] x86: - restore i8259A eoi status on resume [PATCH] i386: Split multi-line printk in oops output. ...

[PATCH] mtrr: Add lock annotations for prepare_set and post_set

2006-09-26T15:48:57Z

The functions prepare_set and post_set in kernel/cpu/mtrr/generic.c wrap the spinlock set_atomicity_lock: prepare_set returns with the lock held, and post_set releases the lock without acquiring it. Add lock annotations to these two functions so that sparse can check callers for lock pairing, and so that sparse will not complain about these functions since they intentionally use locks in this manner. Signed-off-by: Josh Triplett Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

[PATCH] i386/x86-64: New Intel feature flags

2006-09-26T08:52:42Z

Add supplemental SSE3 instructions flag, and Direct Cache Access flag. As described in "Intel Processor idenfication and the CPUID instruction AP485 Sept 2006" AK: also added for x86-64 Signed-off-by: Dave Jones Signed-off-by: Andi Kleen