Hosts the 0x221E linux distro kernel. https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-3.11.y 2013-07-19T22:08:53Z 2013-07-19T22:08:53Z Linus Torvalds 2013-07-19T22:08:53Z urn:sha1:89d0abe3d695103505c025dde6e07b9c3dd772f4 Pull arm64 fixes from Catalin Marinas: - Post -rc1 update to the common reboot infrastructure. - Fixes (user cache maintenance fault handling, !COMPAT compilation, CPU online and interrupt hanlding). * tag 'arm64-stable' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64: arm64: use common reboot infrastructure arm64: mm: don't treat user cache maintenance faults as writes arm64: add '#ifdef CONFIG_COMPAT' for aarch32_break_handler() arm64: Only enable local interrupts after the CPU is marked online 2013-07-19T14:49:42Z Catalin Marinas 2013-07-19T14:08:15Z urn:sha1:53ae3acd4390ffeecb3a11dbd5be347b5a3d98f2 There is a slight chance that (timer) interrupts are triggered before a secondary CPU has been marked online with implications on softirq thread affinity. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Reported-by: Kirill Tkhai <tkhai@yandex.ru> 2013-07-14T23:36:52Z Paul Gortmaker 2013-06-18T14:18:31Z urn:sha1:b8c6453aaf142620c2e1a4c2da24bbb10cb424bf The __cpuinit type of throwaway sections might have made sense some time ago when RAM was more constrained, but now the savings do not offset the cost and complications. For example, the fix in commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time") is a good example of the nasty type of bugs that can be created with improper use of the various __init prefixes. After a discussion on LKML[1] it was decided that cpuinit should go the way of devinit and be phased out. Once all the users are gone, we can then finally remove the macros themselves from linux/init.h. Note that some harmless section mismatch warnings may result, since notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c) are flagged as __cpuinit -- so if we remove the __cpuinit from arch specific callers, we will also get section mismatch warnings. As an intermediate step, we intend to turn the linux/init.h cpuinit content into no-ops as early as possible, since that will get rid of these warnings. In any case, they are temporary and harmless. This removes all the arch/arm64 uses of the __cpuinit macros from all C files. Currently arm64 does not have any __CPUINIT used in assembly files. [1] https://lkml.org/lkml/2013/5/20/589 Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> 2013-04-30T17:10:48Z Linus Torvalds 2013-04-30T17:10:48Z urn:sha1:c9ef713993ba168b38d1a97ea0ab00874f1da022 Pull arm64 update from Catalin Marinas: "Main features: - Versatile Express SoC (model) support - DT files and Kconfig entries (there are no arch/arm64/mach-* directories). The bulk of the code has already been moved to drivers/ as part of the ARM SoC clean-up. - Basic multi-cluster support (CPU logical map initialised from the DT) - Simple earlyprintk support for UART 8250/16550 and FastModel console output - Optimised kernel library bitops and string functions. - Automatic initialisation of the irqchip and clocks via DT" * tag 'arm64-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64: (26 commits) arm64: Use acquire/release semantics instead of explicit DMB arm64: klib: bitops: fix unpredictable stxr usage arm64: vexpress: Enable ARMv8 RTSM model (SoC) support arm64: vexpress: Add dts files for the ARMv8 RTSM models arm64: Survive invalid cpu enable-methods arm64: mm: Correct show_pte behaviour arm64: Fix compat types affecting struct compat_stat arm64: Execute DSB during thread switching for TLB/cache maintenance arm64: compiling issue, need add include/asm/vga.h file arm64: smp: honour #address-size when parsing CPU reg property arm64: Define cmpxchg64 and cmpxchg64_local for outside use arm64: Define readq and writeq for driver module using arm64: Fix task tracing arm64: add explicit symbols to ESR_EL1 decoding arm64: Use irqchip_init() for interrupt controller initialisation arm64: psci: Use the MPIDR values from cpu_logical_map for cpu ids. arm64: klib: Optimised atomic bitops arm64: klib: Optimised string functions arm64: klib: Optimised memory functions arm64: head: match all affinity levels in the pen of the secondaries ... 2013-04-25T16:45:54Z Mark Rutland 2013-04-23T16:22:49Z urn:sha1:39a90ca639db5fcd33064ddf754793ec85764239 Currently, if you pass the kernel a dtb where a cpu node has an unsupported enable-method property (e.g. "not-psci"), it'll explode horribly, as it iterates over the enable_ops array incorrectly. It increments the pointer *at* the current element, rather than incrementing the pointer *to* the current element. As the first two elements pointed to structures that were contiguous in memory, this happened to be equivalent. However the third element is NULL, so when the list is exhausted, smp_get_enable_ops generates the wrong pointer, and dereferences an arbitrary portion of memory, which currently happens to contain zero. This patch fixes this by indirecting the pointer one level, so we iterate over the array elements correctly, avoiding the below panic: Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> 2013-04-25T16:45:43Z Will Deacon 2013-04-22T17:28:55Z urn:sha1:72aea393a2e7c53a951bc581f18a79315f47036b For systems where the top 32-bits of the MPIDR are all zero, we should allow the device-tree to specify an #address-size of 0x1 for the CPU reg property and then zero extend the value there. Without this patch, kvmtool breaks with the recent mpidr parsing code introduced in 4c7aa0021356 ("arm64: kernel: initialise cpu_logical_map from the DT"). Acked-by: Javi Merino <javi.merino@arm.com> Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> 2013-04-08T15:39:24Z Thomas Gleixner 2013-03-21T21:49:39Z urn:sha1:0087298f68a726493a637c4f68d148b31102b0d9 Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Rusty Russell <rusty@rustcorp.com.au> Cc: Paul McKenney <paulmck@linux.vnet.ibm.com> Cc: Peter Zijlstra <peterz@infradead.org> Reviewed-by: Cc: Srivatsa S. Bhat <srivatsa.bhat@linux.vnet.ibm.com> Cc: Magnus Damm <magnus.damm@gmail.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Link: http://lkml.kernel.org/r/20130321215233.887563095@linutronix.de 2013-03-20T17:26:24Z Javi Merino 2012-08-29T08:47:19Z urn:sha1:4c7aa0021356ee91b96cea51b8b7fadebaba489e When booting the kernel, the cpu logical id map must be initialised using device tree data passed by FW or through an embedded blob. This patch parses the reg property in device tree "cpu" nodes, retrieves the corresponding CPUs hardware identifiers (MPIDR) and initialises the cpu logical map accordingly. The device tree HW identifiers are considered valid if all CPU nodes contain a "reg" property, there are no duplicate "reg" entries and the DT defines a CPU node whose "reg" property defines affinity levels that matches those of the boot CPU. The primary CPU is assigned cpu logical number 0 to keep the current convention valid. Based on a0ae02405076ac32bd17ece976e914b5b6075bb0 (ARM: kernel: add device tree init map function). Signed-off-by: Javi Merino <javi.merino@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> 2013-03-20T17:22:12Z Javi Merino 2013-01-31T20:09:04Z urn:sha1:3e98fdacc59bbbdbb659be1a144ccc48ed4860fa Change the prototype of write_pen_release() accordingly and clarify that's holding the hardware id of the secondary that's going to boot. This is in preparation of getting HWIDs parsed from the DT. Signed-off-by: Javi Merino <javi.merino@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> 2013-01-29T16:56:37Z Marc Zyngier 2013-01-02T15:34:50Z urn:sha1:0459ca9b7a9f86d0523e008b79c1fcf1afbd3635 Wire the PSCI implementation into the SMP secondary startup code. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>