kernel.git/arch/arm64/kernel/perf_event.c, branch linux-4.5.y

arm64: perf: add support for Cortex-A72

2015-12-22T14:45:35Z

Cortex-A72 has a PMUv3 implementation that is compatible with the PMU implemented by Cortex-A57. This patch hooks up the new compatible string so that the Cortex-A57 event mappings are used. Signed-off-by: Will Deacon

arm64: perf: add format entry to describe event -> config mapping

2015-12-22T14:45:07Z

It's all very well providing an events directory to userspace that details our events in terms of "event=0xNN", but if we don't define how to encode the "event" field in the perf attr.config, then it's a waste of time. This patch adds a single format entry to describe that the event field occupies the bottom 10 bits of our config field on ARMv8 (PMUv3). Signed-off-by: Will Deacon

arm64: kernel: enforce pmuserenr_el0 initialization and restore

2015-12-21T14:43:04Z

The pmuserenr_el0 register value is architecturally UNKNOWN on reset. Current kernel code resets that register value iff the core pmu device is correctly probed in the kernel. On platforms with missing DT pmu nodes (or disabled perf events in the kernel), the pmu is not probed, therefore the pmuserenr_el0 register is not reset in the kernel, which means that its value retains the reset value that is architecturally UNKNOWN (system may run with eg pmuserenr_el0 == 0x1, which means that PMU counters access is available at EL0, which must be disallowed). This patch adds code that resets pmuserenr_el0 on cold boot and restores it on core resume from shutdown, so that the pmuserenr_el0 setup is always enforced in the kernel. Cc: Cc: Mark Rutland Signed-off-by: Lorenzo Pieralisi Signed-off-by: Will Deacon

arm64: perf: Add event descriptions

2015-11-16T17:09:02Z

Add additional information about the ARM architected hardware events to make counters self describing. This makes the hardware PMUs easier to use as perf list contains possible events instead of users having to refer to documentation like the ARM TRMs. Signed-off-by: Drew Richardson Signed-off-by: Will Deacon

arm64: perf: Convert event enums to #defines

2015-11-16T17:09:02Z

The enums are not necessary and this allows the event values to be used to construct static strings at compile time. Signed-off-by: Drew Richardson Signed-off-by: Will Deacon

arm64: perf: add Cortex-A57 support

2015-10-07T13:25:24Z

The Cortex-A57 PMU supports a few events outside of the required PMUv3 set that are rather useful. This patch adds the event map data for said events. Signed-off-by: Mark Rutland Acked-by: Will Deacon Signed-off-by: Catalin Marinas

arm64: perf: add Cortex-A53 support

2015-10-07T13:25:07Z

The Cortex-A53 PMU supports a few events outside of the required PMUv3 set that are rather useful. This patch adds the event map data for said events. Signed-off-by: Mark Rutland Acked-by: Will Deacon Signed-off-by: Catalin Marinas

arm64: perf: move to shared arm_pmu framework

2015-10-07T13:24:48Z

Now that the arm_pmu framework has been factored out to drivers/perf we can make use of it for arm64, gaining support for heterogeneous PMUs and unifying the two codebases before they diverge further. The as yet unused PMU name for PMUv3 is changed to armv8_pmuv3, matching the style previously applied to the 32-bit PMUs. Signed-off-by: Mark Rutland Acked-by: Will Deacon Signed-off-by: Catalin Marinas

arm64: perf: condense event number maps

2015-07-27T10:08:40Z

Most of the cache events an architecture might support do not map well to those provided by the ARM architecture, and as such most entries in the event number maps are *_UNSUPPORTED. Unfortuantely as 0 is a valid physical event identifier, the *_UNSUPPORTED macros expand to a non-zero value and thus each unsupported event must be explicitly initialised as such. This leads to large diffs when adding support for a new CPU, and makes it difficult to spot the important information. This patch follows arch/arm/ in making use of PERF_*_ALL_UNSUPPORTED macros to initialise all entries to *_UNSUPPORTED before overriding this for the specific events we actually support, resulting in a significant source code reduction. Signed-off-by: Mark Rutland Signed-off-by: Will Deacon

arm64: perf: factor out callchain code

2015-07-27T10:08:39Z

We currently bundle the callchain handling code with the PMU code, despite the fact the two are distinct, and the former can be useful even in the absence of the latter. Follow the example of arch/arm and factor the callchain handling into its own file dependent on CONFIG_PERF_EVENTS rather than CONFIG_HW_PERF_EVENTS. Signed-off-by: Mark Rutland Cc: Will Deacon Signed-off-by: Will Deacon