kernel.git/arch/arm64/kernel/perf_event.c, branch linux-4.13.y

arm64: perf: Extend event config for ARMv8.1

2017-05-30T11:15:14Z

Perf has supported ARMv8.1 feature with 16-bit evtCount filed [see c210ae8 arm64: perf: Extend event mask for ARMv8.1], event config should be extended to 16-bit too, otherwise, if use -e event_name whose event_code is more than 0x3ff, pmu_config_term will return -EINVAL because function pmu_format_max_value depends on event config. This patch extends event config to 16-bit. Signed-off-by: Shaokun Zhang Signed-off-by: Will Deacon

arm64: perf: Ignore exclude_hv when kernel is running in HYP

2017-05-15T17:30:37Z

commit d98ecdaca296 ("arm64: perf: Count EL2 events if the kernel is running in HYP") returns -EINVAL when perf system call perf_event_open is called with exclude_hv != exclude_kernel. This change breaks applications on VHE enabled ARMv8.1 platforms. The issue was observed with HHVM application, which calls perf_event_open with exclude_hv = 1 and exclude_kernel = 0. There is no separate hypervisor privilege level when VHE is enabled, the host kernel runs at EL2. So when VHE is enabled, we should ignore exclude_hv from the application. This behaviour is consistent with PowerPC where the exclude_hv is ignored when the hypervisor is not present and with x86 where this flag is ignored. Signed-off-by: Ganapatrao Kulkarni [will: added comment to justify the behaviour of exclude_hv] Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas

arm64: pmu: Wire-up Cortex A53 L2 cache events and DTLB refills

2017-04-28T14:23:36Z

Add missing L2 cache events: read/write accesses and misses, as well as the DTLB refills. Acked-by: Will Deacon Signed-off-by: Florian Fainelli Signed-off-by: Catalin Marinas

arm64: pmuv3: handle pmuv3+

2017-04-25T14:12:59Z

Commit f1b36dcb5c316c27 ("arm64: pmuv3: handle !PMUv3 when probing") is a little too restrictive, and prevents the use of of backwards compatible PMUv3 extenstions, which have a PMUver value other than 1. For instance, ARMv8.1 PMU extensions (as implemented by ThunderX2) are reported with PMUver value 4. Per the usual ID register principles, at least 0x1-0x7 imply a PMUv3-compatible PMU. It's not currently clear whether 0x8-0xe imply the same. For the time being, treat the value as signed, and with 0x1-0x7 treated as meaning PMUv3 is implemented. This may be relaxed by future patches. Reported-by: Jayachandran C Tested-by: Jayachandran C Acked-by: Will Deacon Signed-off-by: Mark Rutland Signed-off-by: Catalin Marinas

arm64: pmuv3: use arm_pmu ACPI framework

2017-04-11T15:29:54Z

Now that we have a framework to handle the ACPI bits, make the PMUv3 code use this. The framework is a little different to what was originally envisaged, and we can drop some unused support code in the process of moving over to it. Signed-off-by: Mark Rutland Tested-by: Jeremy Linton [will: make armv8_pmu_driver_init static] Signed-off-by: Will Deacon

arm64: pmuv3: handle !PMUv3 when probing

2017-04-11T15:29:54Z

When probing via ACPI, we won't know up-front whether a CPU has a PMUv3 compatible PMU. Thus we need to consult ID registers during probe time. This patch updates our PMUv3 probing code to test for the presence of PMUv3 functionality before touching an PMUv3-specific registers, and before updating the struct arm_pmu with PMUv3 data. When a PMUv3-compatible PMU is not present, probing will return -ENODEV. Signed-off-by: Mark Rutland Cc: Will Deacon Signed-off-by: Will Deacon

KVM: arm64: Fix the issues when guest PMCCFILTR is configured

2016-11-18T09:06:58Z

KVM calls kvm_pmu_set_counter_event_type() when PMCCFILTR is configured. But this function can't deals with PMCCFILTR correctly because the evtCount bits of PMCCFILTR, which is reserved 0, conflits with the SW_INCR event type of other PMXEVTYPER registers. To fix it, when eventsel == 0, this function shouldn't return immediately; instead it needs to check further if select_idx is ARMV8_PMU_CYCLE_IDX. Another issue is that KVM shouldn't copy the eventsel bits of PMCCFILTER blindly to attr.config. Instead it ought to convert the request to the "cpu cycle" event type (i.e. 0x11). To support this patch and to prevent duplicated definitions, a limited set of ARMv8 perf event types were relocated from perf_event.c to asm/perf_event.h. Cc: stable@vger.kernel.org # 4.6+ Acked-by: Will Deacon Signed-off-by: Wei Huang Signed-off-by: Marc Zyngier

arm64: pmu: Hoist pmu platform device name

2016-09-16T16:11:34Z

Move the PMU name into a common header file so it may be referenced by other users. Signed-off-by: Jeremy Linton Signed-off-by: Will Deacon

arm64: pmu: Probe default hw/cache counters

2016-09-16T16:11:33Z

ARMv8 machines can identify the micro/arch defined counters that are available on a machine. Add all these counters to the default armv8 perf map. At run-time disable the counters which are not available on the given PMU. Signed-off-by: Jeremy Linton Acked-by: Will Deacon Signed-off-by: Will Deacon

arm64: pmu: add fallback probe table

2016-09-16T16:11:33Z

In preparation for ACPI support, add a pmu_probe_info table to the arm_pmu_device_probe() call. This table gets used when probing in the absence of a devicetree node for PMU. Signed-off-by: Mark Salter Signed-off-by: Jeremy Linton Signed-off-by: Will Deacon