<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/arch/arm64/include/asm/sysreg.h, branch linux-4.8.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-4.8.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-4.8.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2016-07-01T10:46:00Z</updated>
<entry>
<title>arm64: trap userspace "dc cvau" cache operation on errata-affected core</title>
<updated>2016-07-01T10:46:00Z</updated>
<author>
<name>Andre Przywara</name>
</author>
<published>2016-06-28T17:07:32Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=7dd01aef055792260287c6708daf75aac3918f66'/>
<id>urn:sha1:7dd01aef055792260287c6708daf75aac3918f66</id>
<content type='text'>
The ARM errata 819472, 826319, 827319 and 824069 for affected
Cortex-A53 cores demand to promote "dc cvau" instructions to
"dc civac". Since we allow userspace to also emit those instructions,
we should make sure that "dc cvau" gets promoted there too.
So lets grasp the nettle here and actually trap every userland cache
maintenance instruction once we detect at least one affected core in
the system.
We then emulate the instruction by executing it on behalf of userland,
promoting "dc cvau" to "dc civac" on the way and injecting access
fault back into userspace.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
[catalin.marinas@arm.com: s/set_segfault/arm64_notify_segfault/]
Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
</content>
</entry>
<entry>
<title>arm64: Cleanup SCTLR flags</title>
<updated>2016-04-28T11:05:46Z</updated>
<author>
<name>Geoff Levand</name>
</author>
<published>2016-04-27T16:47:01Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=e7227d0e528f9a96d4a866f43e20dd9b33f0e782'/>
<id>urn:sha1:e7227d0e528f9a96d4a866f43e20dd9b33f0e782</id>
<content type='text'>
We currently have macros defining flags for the arm64 sctlr registers in
both kvm_arm.h and sysreg.h.  To clean things up and simplify move the
definitions of the SCTLR_EL2 flags from kvm_arm.h to sysreg.h, rename any
SCTLR_EL1 or SCTLR_EL2 flags that are common to both registers to be
SCTLR_ELx, with 'x' indicating a common flag, and fixup all files to
include the proper header or to use the new macro names.

Signed-off-by: Geoff Levand &lt;geoff@infradead.org&gt;
[Restored pgtable-hwdef.h include]
Signed-off-by: James Morse &lt;james.morse@arm.com&gt;
Acked-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Signed-off-by: Will Deacon &lt;will.deacon@arm.com&gt;
</content>
</entry>
<entry>
<title>arm64: Add helpers for detecting AArch32 support at EL0</title>
<updated>2016-04-20T11:22:42Z</updated>
<author>
<name>Suzuki K Poulose</name>
</author>
<published>2016-04-18T09:28:34Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=c80aba803a9aa131f997f62a71ab453e456d08a8'/>
<id>urn:sha1:c80aba803a9aa131f997f62a71ab453e456d08a8</id>
<content type='text'>
Adds a helper to extract the support for AArch32 at EL0

Tested-by: Yury Norov &lt;ynorov@caviumnetworks.com&gt;
Signed-off-by: Suzuki K Poulose &lt;suzuki.poulose@arm.com&gt;
Signed-off-by: Will Deacon &lt;will.deacon@arm.com&gt;
</content>
</entry>
<entry>
<title>arm64: cpufeature: append additional id_aa64mmfr2 fields to cpufeature</title>
<updated>2016-04-13T13:49:23Z</updated>
<author>
<name>Kefeng Wang</name>
</author>
<published>2016-03-25T09:30:07Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=7d7b4ae418728916456c6fd03a97ef35345ff30d'/>
<id>urn:sha1:7d7b4ae418728916456c6fd03a97ef35345ff30d</id>
<content type='text'>
There are some new cpu features which can be identified by id_aa64mmfr2,
this patch appends all fields of it.

Signed-off-by: Kefeng Wang &lt;wangkefeng.wang@huawei.com&gt;
Signed-off-by: Will Deacon &lt;will.deacon@arm.com&gt;
</content>
</entry>
<entry>
<title>arm64: kvm: 4.6-rc1: Fix VTCR_EL2 VS setting</title>
<updated>2016-03-30T20:09:15Z</updated>
<author>
<name>Suzuki K Poulose</name>
</author>
<published>2016-03-30T13:33:59Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=cb678d6016510cc8c6572dd9f426fe74dd4eda84'/>
<id>urn:sha1:cb678d6016510cc8c6572dd9f426fe74dd4eda84</id>
<content type='text'>
When we detect support for 16bit VMID in ID_AA64MMFR1, we set the
VTCR_EL2_VS field to 1 to make use of 16bit vmids. But, with
commit 3a3604bc5eb4 ("arm64: KVM: Switch to C-based stage2 init")
this is broken and we corrupt VTCR_EL2:T0SZ instead of updating the VS
field. VTCR_EL2_VS was actually defined to the field shift (19) and
not the real value for VS. This patch fixes the issue.

Fixes: commit 3a3604bc5eb4 ("arm64: KVM: Switch to C-based stage2 init")
Cc: Christoffer Dall &lt;christoffer.dall@linaro.org&gt;
Cc: Mark Rutland &lt;mark.rutland@arm.com&gt;
Acked-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Signed-off-by: Suzuki K Poulose &lt;suzuki.poulose@arm.com&gt;
Signed-off-by: Christoffer Dall &lt;christoffer.dall@linaro.org&gt;
</content>
</entry>
<entry>
<title>arm64: kernel: Add support for User Access Override</title>
<updated>2016-02-18T17:27:04Z</updated>
<author>
<name>James Morse</name>
</author>
<published>2016-02-05T14:58:48Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=57f4959bad0a154aeca125b7d38d1d9471a12422'/>
<id>urn:sha1:57f4959bad0a154aeca125b7d38d1d9471a12422</id>
<content type='text'>
'User Access Override' is a new ARMv8.2 feature which allows the
unprivileged load and store instructions to be overridden to behave in
the normal way.

This patch converts {get,put}_user() and friends to use ldtr*/sttr*
instructions - so that they can only access EL0 memory, then enables
UAO when fs==KERNEL_DS so that these functions can access kernel memory.

This allows user space's read/write permissions to be checked against the
page tables, instead of testing addr&lt;USER_DS, then using the kernel's
read/write permissions.

Signed-off-by: James Morse &lt;james.morse@arm.com&gt;
[catalin.marinas@arm.com: move uao_thread_switch() above dsb()]
Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
</content>
</entry>
<entry>
<title>arm64: add ARMv8.2 id_aa64mmfr2 boiler plate</title>
<updated>2016-02-18T12:00:01Z</updated>
<author>
<name>James Morse</name>
</author>
<published>2016-02-05T14:58:47Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=406e308770a92bd33995b2e5b681e86358328bb0'/>
<id>urn:sha1:406e308770a92bd33995b2e5b681e86358328bb0</id>
<content type='text'>
ARMv8.2 adds a new feature register id_aa64mmfr2. This patch adds the
cpu feature boiler plate used by the actual features in later patches.

Signed-off-by: James Morse &lt;james.morse@arm.com&gt;
Reviewed-by: Suzuki K Poulose &lt;suzuki.poulose@arm.com&gt;
Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
</content>
</entry>
<entry>
<title>arm64: use local label prefixes for __reg_num symbols</title>
<updated>2016-02-16T18:39:58Z</updated>
<author>
<name>Ard Biesheuvel</name>
</author>
<published>2016-02-15T08:51:49Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=7abc7d833c9eb16efc8a59239d3771a6e30be367'/>
<id>urn:sha1:7abc7d833c9eb16efc8a59239d3771a6e30be367</id>
<content type='text'>
The __reg_num_xNN symbols that are used to implement the msr_s and
mrs_s macros are recorded in the ELF metadata of each object file.
This does not affect the size of the final binary, but it does clutter
the output of tools like readelf, i.e.,

  $ readelf -a vmlinux |grep -c __reg_num_x
  50976

So let's use symbols with the .L prefix, these are strictly local,
and don't end up in the object files.

  $ readelf -a vmlinux |grep -c __reg_num_x
  0

Acked-by: Will Deacon &lt;will.deacon@arm.com&gt;
Signed-off-by: Ard Biesheuvel &lt;ard.biesheuvel@linaro.org&gt;
Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
</content>
</entry>
<entry>
<title>arm64: Add macros to read/write system registers</title>
<updated>2015-12-14T11:30:38Z</updated>
<author>
<name>Mark Rutland</name>
</author>
<published>2015-11-05T15:09:17Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=3600c2fdc09a43a30909743569e35a29121602ed'/>
<id>urn:sha1:3600c2fdc09a43a30909743569e35a29121602ed</id>
<content type='text'>
Rather than crafting custom macros for reading/writing each system
register provide generics accessors, read_sysreg and write_sysreg, for
this purpose.

Signed-off-by: Mark Rutland &lt;mark.rutland@arm.com&gt;
Acked-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Cc: Suzuki Poulose &lt;suzuki.poulose@arm.com&gt;
Cc: Will Deacon &lt;will.deacon@arm.com&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
</content>
</entry>
<entry>
<title>arm64: Keep track of CPU feature registers</title>
<updated>2015-10-21T14:35:37Z</updated>
<author>
<name>Suzuki K. Poulose</name>
</author>
<published>2015-10-19T13:24:45Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=3c739b57108436211c7f798ba3de0bb0cd8ef469'/>
<id>urn:sha1:3c739b57108436211c7f798ba3de0bb0cd8ef469</id>
<content type='text'>
This patch adds an infrastructure to keep track of the CPU feature
registers on the system. For each register, the infrastructure keeps
track of the system wide safe value of the feature bits. Also, tracks
the which fields of a register should be matched strictly across all
the CPUs on the system for the SANITY check infrastructure.

The feature bits are classified into following 3 types depending on
the implication of the possible values. This information is used to
decide the safe value for a feature.

LOWER_SAFE  - The smaller value is safer
HIGHER_SAFE - The bigger value is safer
EXACT       - We can't decide between the two, so a predefined safe_value is used.

This infrastructure will be later used to make better decisions for:

 - Kernel features (e.g, KVM, Debug)
 - SANITY Check
 - CPU capability
 - ELF HWCAP
 - Exposing CPU Feature register to userspace.

Signed-off-by: Suzuki K. Poulose &lt;suzuki.poulose@arm.com&gt;
Tested-by: Dave Martin &lt;Dave.Martin@arm.com&gt;
[catalin.marinas@arm.com: whitespace fix]
Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
</content>
</entry>
</feed>
