kernel.git/arch/arm64/include/asm/sysreg.h, branch linux-4.13.y

arm64: sysreg: Fix unprotected macro argmuent in write_sysreg

2017-07-26T08:28:18Z

write_sysreg() may misparse the value argument because it is used without parentheses to protect it. This patch adds the ( ) in order to avoid any surprises. Acked-by: Mark Rutland Signed-off-by: Dave Martin [will: same change to write_sysreg_s] Signed-off-by: Will Deacon

arm64: Remove a redundancy in sysreg.h

2017-06-22T16:38:42Z

This is really trivial; there is a dup (1 << 16) in the code Acked-by: Will Deacon Signed-off-by: Stefan Traby Signed-off-by: Marc Zyngier

arm64/kvm: vgic: use SYS_DESC()

2017-06-15T08:45:08Z

Almost all of the arm64 KVM code uses the sysreg mnemonics for AArch64 register descriptions. Move the last straggler over. To match what we do for SYS_ICH_AP*R*_EL2, the SYS_ICC_AP*R*_EL1 mnemonics are expanded in . Signed-off-by: Mark Rutland Cc: Catalin Marinas Cc: Marc Zyngier Cc: kvmarm@lists.cs.columbia.edu Acked-by: Christoffer Dall Acked-by: Will Deacon Signed-off-by: Christoffer Dall

arm64/kvm: sysreg: fix typo'd SYS_ICC_IGRPEN*_EL1

2017-06-15T08:45:07Z

Per ARM DDI 0487B.a, the registers are named ICC_IGRPEN*_EL1 rather than ICC_GRPEN*_EL1. Correct our mnemonics and comments to match, before we add more GICv3 register definitions. Signed-off-by: Mark Rutland Cc: Catalin Marinas Cc: Marc Zyngier Cc: kvmarm@lists.cs.columbia.edu Acked-by: Christoffer Dall Acked-by: Will Deacon Signed-off-by: Christoffer Dall

KVM: arm64: vgic-v3: Add ICV_RPR_EL1 handler

2017-06-15T08:45:05Z

Add a handler for reading the guest's view of the ICV_RPR_EL1 register, returning the highest active priority. Tested-by: Alexander Graf Acked-by: David Daney Acked-by: Christoffer Dall Reviewed-by: Eric Auger Signed-off-by: Marc Zyngier Signed-off-by: Christoffer Dall

KVM: arm64: vgic-v3: Add misc Group-0 handlers

2017-06-15T08:45:02Z

A number of Group-0 registers can be handled by the same accessors as that of Group-1, so let's add the required system register encodings and catch them in the dispatching function. Tested-by: Alexander Graf Acked-by: David Daney Acked-by: Christoffer Dall Reviewed-by: Eric Auger Signed-off-by: Marc Zyngier Signed-off-by: Christoffer Dall

KVM: arm64: vgic-v3: Add ICV_IGNREN0_EL1 handler

2017-06-15T08:45:02Z

Add a handler for reading/writing the guest's view of the ICC_IGRPEN0_EL1 register, which is located in the ICH_VMCR_EL2.VENG0 field. Tested-by: Alexander Graf Acked-by: David Daney Reviewed-by: Eric Auger Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier Signed-off-by: Christoffer Dall

KVM: arm64: vgic-v3: Add ICV_BPR0_EL1 handler

2017-06-15T08:45:02Z

Add a handler for reading/writing the guest's view of the ICC_BPR0_EL1 register, which is located in the ICH_VMCR_EL2.BPR0 field. Tested-by: Alexander Graf Acked-by: David Daney Reviewed-by: Eric Auger Signed-off-by: Marc Zyngier Reviewed-by: Christoffer Dall Signed-off-by: Christoffer Dall

KVM: arm64: vgic-v3: Add ICV_HPPIR1_EL1 handler

2017-06-15T08:45:01Z

Add a handler for reading the guest's view of the ICV_HPPIR1_EL1 register. This is a simple parsing of the available LRs, extracting the highest available interrupt. Tested-by: Alexander Graf Acked-by: David Daney Reviewed-by: Eric Auger Signed-off-by: Marc Zyngier Reviewed-by: Christoffer Dall Signed-off-by: Christoffer Dall

KVM: arm64: vgic-v3: Add ICV_AP1Rn_EL1 handler

2017-06-15T08:45:00Z

Add a handler for reading/writing the guest's view of the ICV_AP1Rn_EL1 registers. We just map them to the corresponding ICH_AP1Rn_EL2 registers. Tested-by: Alexander Graf Acked-by: David Daney Reviewed-by: Eric Auger Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier Signed-off-by: Christoffer Dall