<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/arch/arm64/include/asm/pgtable.h, branch linux-3.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-3.17.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-3.17.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2014-07-24T09:25:42Z</updated>
<entry>
<title>arm64: Fix barriers used for page table modifications</title>
<updated>2014-07-24T09:25:42Z</updated>
<author>
<name>Catalin Marinas</name>
</author>
<published>2014-06-09T10:55:03Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=7f0b1bf04511348995d6fce38c87c98a3b5cb781'/>
<id>urn:sha1:7f0b1bf04511348995d6fce38c87c98a3b5cb781</id>
<content type='text'>
The architecture specification states that both DSB and ISB are required
between page table modifications and subsequent memory accesses using the
corresponding virtual address. When TLB invalidation takes place, the
tlb_flush_* functions already have the necessary barriers. However, there are
other functions like create_mapping() for which this is not the case.

The patch adds the DSB+ISB instructions in the set_pte() function for
valid kernel mappings. The invalid pte case is handled by tlb_flush_*
and the user mappings in general have a corresponding update_mmu_cache()
call containing a DSB. Even when update_mmu_cache() isn't called, the
kernel can still cope with an unlikely spurious page fault by
re-executing the instruction.

In addition, the set_pmd, set_pud() functions gain an ISB for
architecture compliance when block mappings are created.

Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Reported-by: Leif Lindholm &lt;leif.lindholm@linaro.org&gt;
Acked-by: Steve Capper &lt;steve.capper@linaro.org&gt;
Cc: Will Deacon &lt;will.deacon@arm.com&gt;
Cc: &lt;stable@vger.kernel.org&gt;
</content>
</entry>
<entry>
<title>arm64: asm/pgtable.h pmd/pud definitions clean-up</title>
<updated>2014-07-23T14:28:10Z</updated>
<author>
<name>Catalin Marinas</name>
</author>
<published>2014-07-21T13:52:49Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=7078db46215f9137801a122f87ac31c504220a94'/>
<id>urn:sha1:7078db46215f9137801a122f87ac31c504220a94</id>
<content type='text'>
Non-functional change to group together the pmd/pud definitions and
reduce the amount of #if CONFIG_ARM64_PGTABLE_LEVELS.

Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Tested-by: Jungseok Lee &lt;jungseoklee85@gmail.com&gt;
</content>
</entry>
<entry>
<title>arm64: Determine the vmalloc/vmemmap space at build time based on VA_BITS</title>
<updated>2014-07-23T14:28:05Z</updated>
<author>
<name>Catalin Marinas</name>
</author>
<published>2014-07-16T16:42:43Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=08375198b01001c0e43bdd580104b16b019a3754'/>
<id>urn:sha1:08375198b01001c0e43bdd580104b16b019a3754</id>
<content type='text'>
Rather than guessing what the maximum vmmemap space should be, this
patch allows the calculation based on the VA_BITS and sizeof(struct
page). The vmalloc space extends to the beginning of the vmemmap space.

Since the virtual kernel memory layout now depends on the build
configuration, this patch removes the detailed description in
Documentation/arm64/memory.txt in favour of information printed during
kernel booting.

Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Tested-by: Jungseok Lee &lt;jungseoklee85@gmail.com&gt;
</content>
</entry>
<entry>
<title>arm64: Convert bool ARM64_x_LEVELS to int ARM64_PGTABLE_LEVELS</title>
<updated>2014-07-23T14:27:46Z</updated>
<author>
<name>Catalin Marinas</name>
</author>
<published>2014-07-15T14:37:21Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=abe669d7e1a8f9163eb7e8e153e7257d38c1ba3e'/>
<id>urn:sha1:abe669d7e1a8f9163eb7e8e153e7257d38c1ba3e</id>
<content type='text'>
Rather than having several Kconfig options, define int
ARM64_PGTABLE_LEVELS which will be also useful in converting some of the
pgtable macros.

Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Tested-by: Jungseok Lee &lt;jungseoklee85@gmail.com&gt;
</content>
</entry>
<entry>
<title>arm64: mm: Implement 4 levels of translation tables</title>
<updated>2014-07-23T14:27:40Z</updated>
<author>
<name>Jungseok Lee</name>
</author>
<published>2014-05-12T09:40:51Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=c79b954bf6c006f2d3dd9d01f231abeead13a410'/>
<id>urn:sha1:c79b954bf6c006f2d3dd9d01f231abeead13a410</id>
<content type='text'>
This patch implements 4 levels of translation tables since 3 levels
of page tables with 4KB pages cannot support 40-bit physical address
space described in [1] due to the following issue.

It is a restriction that kernel logical memory map with 4KB + 3 levels
(0xffffffc000000000-0xffffffffffffffff) cannot cover RAM region from
544GB to 1024GB in [1]. Specifically, ARM64 kernel fails to create
mapping for this region in map_mem function since __phys_to_virt for
this region reaches to address overflow.

If SoC design follows the document, [1], over 32GB RAM would be placed
from 544GB. Even 64GB system is supposed to use the region from 544GB
to 576GB for only 32GB RAM. Naturally, it would reach to enable 4 levels
of page tables to avoid hacking __virt_to_phys and __phys_to_virt.

However, it is recommended 4 levels of page table should be only enabled
if memory map is too sparse or there is about 512GB RAM.

References
----------
[1]: Principles of ARM Memory Maps, White Paper, Issue C

Signed-off-by: Jungseok Lee &lt;jays.lee@samsung.com&gt;
Reviewed-by: Sungjinn Chung &lt;sungjinn.chung@samsung.com&gt;
Acked-by: Kukjin Kim &lt;kgene.kim@samsung.com&gt;
Reviewed-by: Christoffer Dall &lt;christoffer.dall@linaro.org&gt;
Reviewed-by: Steve Capper &lt;steve.capper@linaro.org&gt;
[catalin.marinas@arm.com: MEMBLOCK_INITIAL_LIMIT removed, same as PUD_SIZE]
[catalin.marinas@arm.com: early_ioremap_init() updated for 4 levels]
[catalin.marinas@arm.com: 48-bit VA depends on BROKEN until KVM is fixed]
Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Tested-by: Jungseok Lee &lt;jungseoklee85@gmail.com&gt;
</content>
</entry>
<entry>
<title>arm64: Introduce VA_BITS and translation level options</title>
<updated>2014-07-23T14:27:21Z</updated>
<author>
<name>Jungseok Lee</name>
</author>
<published>2014-05-12T09:40:38Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=e41ceed035966d593ae34c3de33924965a6b9fba'/>
<id>urn:sha1:e41ceed035966d593ae34c3de33924965a6b9fba</id>
<content type='text'>
This patch adds virtual address space size and a level of translation
tables to kernel configuration. It facilicates introduction of
different MMU options, such as 4KB + 4 levels, 16KB + 4 levels and
64KB + 3 levels, easily.

The idea is based on the discussion with Catalin Marinas:
http://www.spinics.net/linux/lists/arm-kernel/msg319552.html

Signed-off-by: Jungseok Lee &lt;jays.lee@samsung.com&gt;
Reviewed-by: Sungjinn Chung &lt;sungjinn.chung@samsung.com&gt;
Acked-by: Kukjin Kim &lt;kgene.kim@samsung.com&gt;
Reviewed-by: Christoffer Dall &lt;christoffer.dall@linaro.org&gt;
Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Tested-by: Jungseok Lee &lt;jungseoklee85@gmail.com&gt;
</content>
</entry>
<entry>
<title>arm64: Remove duplicate (SWAPPER|IDMAP)_DIR_SIZE definitions</title>
<updated>2014-07-17T15:02:42Z</updated>
<author>
<name>Catalin Marinas</name>
</author>
<published>2014-07-15T14:46:02Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=b2f8c07bcb7d1a3575f41444d2d8048d0c922762'/>
<id>urn:sha1:b2f8c07bcb7d1a3575f41444d2d8048d0c922762</id>
<content type='text'>
Just keep the asm/page.h definition as this is included in vmlinux.lds.S
as well.

Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Acked-by: Mark Rutland &lt;mark.rutland@arm.com&gt;
</content>
</entry>
<entry>
<title>arm64: mm: Fix horrendous config typo</title>
<updated>2014-07-04T13:22:30Z</updated>
<author>
<name>Steve Capper</name>
</author>
<published>2014-06-25T07:41:45Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=f3b766a26dd490026b9eb91a9136ade9f49fc674'/>
<id>urn:sha1:f3b766a26dd490026b9eb91a9136ade9f49fc674</id>
<content type='text'>
The define ARM64_64K_PAGES is tested for rather than
CONFIG_ARM64_64K_PAGES. Correct that typo here.

Signed-off-by: Steve Capper &lt;steve.capper@linaro.org&gt;
Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
</content>
</entry>
<entry>
<title>arm64: mm: remove broken &amp;= operator from pmd_mknotpresent</title>
<updated>2014-06-18T15:34:30Z</updated>
<author>
<name>Will Deacon</name>
</author>
<published>2014-06-18T13:06:27Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=e3a920afc3482e954834a4ed95908c4bc5e4c000'/>
<id>urn:sha1:e3a920afc3482e954834a4ed95908c4bc5e4c000</id>
<content type='text'>
This should be a plain old '&amp;' and could easily lead to undefined
behaviour if the target of a pmd_mknotpresent invocation was the same
as the parameter.

Fixes: 9c7e535fcc17 (arm64: mm: Route pmd thp functions through pte equivalents)
Signed-off-by: Will Deacon &lt;will.deacon@arm.com&gt;
Cc: &lt;stable@vger.kernel.org&gt; # v3.15
Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux into next</title>
<updated>2014-06-06T17:43:28Z</updated>
<author>
<name>Linus Torvalds</name>
</author>
<published>2014-06-06T17:43:28Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=cc07aabc53978ae09a1d539237189f7c9841060a'/>
<id>urn:sha1:cc07aabc53978ae09a1d539237189f7c9841060a</id>
<content type='text'>
Pull arm64 updates from Catalin Marinas:
 - Optimised assembly string/memory routines (based on the AArch64
   Cortex Strings library contributed to glibc but re-licensed under
   GPLv2)
 - Optimised crypto algorithms making use of the ARMv8 crypto extensions
   (together with kernel API for using FPSIMD instructions in interrupt
   context)
 - Ftrace support
 - CPU topology parsing from DT
 - ESR_EL1 (Exception Syndrome Register) exposed to user space signal
   handlers for SIGSEGV/SIGBUS (useful to emulation tools like Qemu)
 - 1GB section linear mapping if applicable
 - Barriers usage clean-up
 - Default pgprot clean-up

Conflicts as per Catalin.

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (57 commits)
  arm64: kernel: initialize broadcast hrtimer based clock event device
  arm64: ftrace: Add system call tracepoint
  arm64: ftrace: Add CALLER_ADDRx macros
  arm64: ftrace: Add dynamic ftrace support
  arm64: Add ftrace support
  ftrace: Add arm64 support to recordmcount
  arm64: Add 'notrace' attribute to unwind_frame() for ftrace
  arm64: add __ASSEMBLY__ in asm/insn.h
  arm64: Fix linker script entry point
  arm64: lib: Implement optimized string length routines
  arm64: lib: Implement optimized string compare routines
  arm64: lib: Implement optimized memcmp routine
  arm64: lib: Implement optimized memset routine
  arm64: lib: Implement optimized memmove routine
  arm64: lib: Implement optimized memcpy routine
  arm64: defconfig: enable a few more common/useful options in defconfig
  ftrace: Make CALLER_ADDRx macros more generic
  arm64: Fix deadlock scenario with smp_send_stop()
  arm64: Fix machine_shutdown() definition
  arm64: Support arch_irq_work_raise() via self IPIs
  ...
</content>
</entry>
</feed>
