kernel.git/arch/arm/kernel/hw_breakpoint.c, branch linux-3.2.y

ARM: 8634/1: hw_breakpoint: blacklist Scorpion CPUs

2017-03-16T02:18:42Z

commit ddc37832a1349f474c4532de381498020ed71d31 upstream. On APQ8060, the kernel crashes in arch_hw_breakpoint_init, taking an undefined instruction trap within write_wb_reg. This is because Scorpion CPUs erroneously appear to set DBGPRSR.SPD when WFI is issued, even if the core is not powered down. When DBGPRSR.SPD is set, breakpoint and watchpoint registers are treated as undefined. It's possible to trigger similar crashes later on from userspace, by requesting the kernel to install a breakpoint or watchpoint, as we can go idle at any point between the reset of the debug registers and their later use. This has always been the case. Given that this has always been broken, no-one has complained until now, and there is no clear workaround, disable hardware breakpoints and watchpoints on Scorpion to avoid these issues. Signed-off-by: Mark Rutland Reported-by: Linus Walleij Reviewed-by: Stephen Boyd Acked-by: Will Deacon Cc: Russell King Signed-off-by: Russell King [bwh: Backported to 3.2: - Open-code read_cpuid_part() - Adjust context] Signed-off-by: Ben Hutchings

ARM: 7496/1: hw_breakpoint: don't rely on dfsr to show watchpoint access type

2012-09-19T14:05:04Z

commit bf8801145c01ab600f8df66e8c879ac642fa5846 upstream. From ARM debug architecture v7.1 onwards, a watchpoint exception causes the DFAR to be updated with the faulting data address. However, DFSR.WnR takes an UNKNOWN value and therefore cannot be used in general to determine the access type that triggered the watchpoint. This patch forbids watchpoints without an overflow handler from specifying a specific access type (load/store). Those with overflow handlers must be able to handle false positives potentially triggered by a watchpoint of a different access type on the same address. For SIGTRAP-based handlers (i.e. ptrace), this should have no impact. Signed-off-by: Will Deacon Signed-off-by: Russell King Signed-off-by: Ben Hutchings

ARM: 7127/1: hw_breakpoint: skip v7-specific reset on v6 cores

2011-10-08T09:05:34Z

ARMv6 cores do not implement the DBGOSLAR register, so we don't need to try and clear it on boot. Furthermore, the VCR is zeroed out of reset, so we don't need to zero it explicitly when a CPU comes online. Tested-by: Marc Zyngier Signed-off-by: Will Deacon Signed-off-by: Russell King

ARM: hw_breakpoint: reduce the number of WARN_ONCE invocations

2011-08-31T09:42:48Z

The ARM hw_breakpoint backend is currently a bit too noisy when things start to go awry. This patch removes a couple of over-zealous WARN_ONCE invocations and replaces then with pr_warnings instead. Signed-off-by: Will Deacon

ARM: hw_breakpoint: trap undef instruction exceptions in reset_ctrl_regs

2011-08-31T09:42:48Z

The ARM debug registers can only be accessed if the DBGSWENABLE signal to the core is driven HIGH by the DAP. The architecture does not provide a way to detect the value of this signal, so the best we can do is register an undef_hook to trap debug register co-processor accesses and then fail if the trap is taken. Signed-off-by: Will Deacon

ARM: hw_breakpoint: add support for multiple watchpoints

2011-08-31T09:42:48Z

ARM debug architecture 7.1 mandates that the DFAR is updated on a watchpoint debug exception to contain the faulting virtual address of the memory access. This allows us to determine which watchpoints have fired and therefore report useful information to userspace. This patch adds support for using the DFAR in the watchpoint handler, which allows us to support multiple watchpoints on CPUs implementing the new debug architecture. Signed-off-by: Will Deacon

ARM: hw_breakpoint: reserve one breakpoint for watchpoint stepping

2011-08-31T09:42:48Z

The current hw_breakpoint code on ARM reserves 1 breakpoint for each watchpoint that is available. Since debug architectures prior to 7.1 are restricted to 1 watchpoint anyway, only one breakpoint was ever reserved. This patch changes the reservation strategy so that a single breakpoint is reserved, regardless of the number of watchpoints. This is in preparation for multiple-watchpoint support on debug architectures from 7.1 onwards. Signed-off-by: Will Deacon

ARM: hw_breakpoint: add initial Cortex-A15 (debug v7.1) support

2011-08-31T09:42:47Z

This patch adds initial support for Cortex-A15 (debug architecture v7.1) to the hw_breakpoint ARM backend. Signed-off-by: Will Deacon

ARM: entry: avoid enabling interrupts in prefetch/data abort handlers

2011-07-02T09:56:00Z

Avoid enabling interrupts if the parent context had interrupts enabled in the abort handler assembly code, and move this into the breakpoint/ page/alignment fault handlers instead. This gets rid of some special-casing for the breakpoint fault handlers from the low level abort handler path. Acked-by: Will Deacon Signed-off-by: Russell King

ARM: 6864/1: hw_breakpoint: clear DBGVCR out of reset

2011-04-10T20:13:35Z

The DBGVCR, used for configuring vector catch debug events, is UNKNOWN out of reset on ARMv7. When enabling monitor mode, this must be zeroed to avoid UNPREDICTABLE behaviour. This patch adds the zeroing code to the debug reset path. Cc: stable Reported-by: Stepan Moskovchenko Signed-off-by: Will Deacon Signed-off-by: Russell King