kernel.git/arch/arm/include/asm/mach, branch linux-2.6.30.y

[ARM] 5422/1: ARM: MMU: add a Non-cacheable Normal executable memory type

2009-03-12T19:25:02Z

This patch adds a Non-cacheable Normal ARM executable memory type, MT_MEMORY_NONCACHED. On OMAP3, this is used for rapid dynamic voltage/frequency scaling in the VDD2 voltage domain. OMAP3's SDRAM controller (SDRC) is in the VDD2 voltage domain, and its clock frequency must change along with voltage. The SDRC clock change code cannot run from SDRAM itself, since SDRAM accesses are paused during the clock change. So the current implementation of the DVFS code executes from OMAP on-chip SRAM, aka "OCM RAM." If the OCM RAM pages are marked as Cacheable, the ARM cache controller will attempt to flush dirty cache lines to the SDRC, so it can fill those lines with OCM RAM instruction code. The problem is that the SDRC is paused during DVFS, and so any SDRAM access causes the ARM MPU subsystem to hang. TI's original solution to this problem was to mark the OCM RAM sections as Strongly Ordered memory, thus preventing caching. This is overkill: since the memory is marked as non-bufferable, OCM RAM writes become needlessly slow. The idea of "Strongly Ordered SRAM" is also conceptually disturbing. Previous LAKML list discussion is here: http://www.spinics.net/lists/arm-kernel/msg54312.html This memory type MT_MEMORY_NONCACHED is used for OCM RAM by a future patch. Cc: Richard Woodruff Signed-off-by: Paul Walmsley Signed-off-by: Russell King

Merge branch 'dma' into devel

2009-02-21T21:42:50Z

Conflicts: arch/arm/plat-mxc/dma-mx1-mx2.c

[ARM] dma: move IOMD and floppy DMA structures to RiscPC DMA code

2009-02-21T21:36:22Z

There's no point these being in a generic include file when they're only used in arch/arm/mach-rpc/dma.c. Signed-off-by: Russell King

PCI: arm: use generic INTx swizzle from PCI core

2009-01-07T19:13:13Z

Use the generic pci_common_swizzle() instead of arch-specific code. Signed-off-by: Bjorn Helgaas Signed-off-by: Jesse Barnes

[ARM] dma: remove dmamode_t typedef

2009-01-02T12:34:55Z

Signed-off-by: Russell King

[ARM] dma: constify dma controller name and dma ops

2008-12-11T14:52:42Z

Signed-off-by: Russell King

[ARM] dma: move RiscPC specific DMA data out of dma_struct

2008-12-11T14:35:57Z

Separate the RiscPC specific (IOMD and floppy FIQ) data out of the core DMA structure by making the IOMD and floppy DMA supersets. Signed-off-by: Russell King

[ARM] dma: rejig DMA initialization

2008-12-11T14:32:43Z

Rather than having the central DMA multiplexer call the architecture specific DMA initialization function, have each architecture DMA initialization function use core_initcall(), and register each DMA channel separately with the multiplexer. This removes the array of dma structures in the central multiplexer, replacing it with an array of pointers instead; this is more flexible since it allows the drivers to wrap the DMA structure (eventually allowing us to transition non-ISA DMA drivers away.) Signed-off-by: Russell King

[ARM] dma: remove dmach_t typedef

2008-12-08T15:58:50Z

Remove a pointless integer typedef. Signed-off-by: Russell King

[ARM] iop: iop3xx needs registers mapped uncached+unbuffered

2008-11-09T11:18:36Z

Mikael Pettersson reported: The 2.6.28-rc kernels fail to detect PCI device 0000:00:01.0 (the first ethernet port) on my Thecus n2100 XScale box. There is however still a strange "ghost" device that gets partially detected in 2.6.28-rc2 vanilla. The IOP321 manual says: The user designates the memory region containing the OCCDR as non-cacheable and non-bufferable from the IntelR XScaleTM core. This guarantees that all load/stores to the OCCDR are only of DWORD quantities. Ensure that the OCCDR is so mapped. Signed-off-by: Russell King