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<title>kernel.git/arch/arm/include/asm/fixmap.h, branch linux-3.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-3.17.y</id>
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<updated>2014-04-23T10:09:42Z</updated>
<entry>
<title>ARM: 8031/2: change fixmap mapping region to support 32 CPUs</title>
<updated>2014-04-23T10:09:42Z</updated>
<author>
<name>Liu Hua</name>
</author>
<published>2014-04-18T08:43:32Z</published>
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<id>urn:sha1:a05e54c103b0b8e1dab5d04b411f1d48387c4903</id>
<content type='text'>
In 32-bit ARM systems, the fixmap mapping region can support no more
than 14 CPUs(total: 896k; one CPU: 64K). And we can configure NR_CPUS
up to 32. So there is a mismatch.

This patch moves fixmapping region downwards to region 0xffc00000-
0xffe00000. Then the fixmap mapping region can support up to 32 CPUs.

Reviewed-by: Nicolas Pitre &lt;nico@linaro.org&gt;
Signed-off-by: Liu Hua &lt;sdu.liu@huawei.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
</entry>
<entry>
<title>ARM: 8031/1: fixmap: remove FIX_KMAP_BEGIN and FIX_KMAP_END</title>
<updated>2014-04-23T10:09:27Z</updated>
<author>
<name>Liu Hua</name>
</author>
<published>2014-04-18T08:27:01Z</published>
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<id>urn:sha1:4221e2e6b3160e4b558df14fa79f025c0e277935</id>
<content type='text'>
It seems that these two macros are not used by non architecture
specific code. And on ARM FIX_KMAP_BEGIN equals zero.

This patch removes these two macros. Instead, using FIX_KMAP_NR_PTES to
tell the pte number belonged to fixmap mapping region. The code will
become clearer when I introduce a bugfix on fixmap mapping region.

Reviewed-by: Nicolas Pitre &lt;nico@linaro.org&gt;
Signed-off-by: Liu Hua &lt;sdu.liu@huawei.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
</entry>
<entry>
<title>[ARM] fixmap support</title>
<updated>2009-03-16T01:01:20Z</updated>
<author>
<name>Nicolas Pitre</name>
</author>
<published>2008-09-16T17:05:53Z</published>
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<id>urn:sha1:5f0fbf9ecaf354fa4bbf266fffdea2ea3d14a0ed</id>
<content type='text'>
This is the minimum fixmap interface expected to be implemented by
architectures supporting highmem.

We have a second level page table already allocated and covering
0xfff00000-0xffffffff because the exception vector page is located
at 0xffff0000, and various cache tricks already use some entries above
0xffff0000.  Therefore the PTEs covering 0xfff00000-0xfffeffff are free
to be used.

However the XScale cache flushing code already uses virtual addresses
between 0xfffe0000 and 0xfffeffff.

So this reserves the 0xfff00000-0xfffdffff range for fixmap stuff.

The Documentation/arm/memory.txt information is updated accordingly,
including the information about the actual top of DMA memory mapping
region which didn't match the code.

Signed-off-by: Nicolas Pitre &lt;nico@marvell.com&gt;
</content>
</entry>
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