kernel.git/arch/arc/mm/cache.c, branch linux-4.12.y

ARCv2: PAE40: set MSB even if !CONFIG_ARC_HAS_PAE40 but PAE exists in SoC

2017-08-30T08:26:32Z

commit b5ddb6d54729d814356937572d6c9b599f10c29f upstream. PAE40 confiuration in hardware extends some of the address registers for TLB/cache ops to 2 words. So far kernel was NOT setting the higher word if feature was not enabled in software which is wrong. Those need to be set to 0 in such case. Normally this would be done in the cache flush / tlb ops, however since these registers only exist conditionally, this would have to be conditional to a flag being set on boot which is expensive/ugly - specially for the more common case of PAE exists but not in use. Optimize that by zero'ing them once at boot - nobody will write to them afterwards Signed-off-by: Vineet Gupta Signed-off-by: Greg Kroah-Hartman

ARCv2: PAE40: Explicitly set MSB counterpart of SLC region ops addresses

2017-08-30T08:26:32Z

commit 7d79cee2c6540ea64dd917a14e2fd63d4ac3d3c0 upstream. It is necessary to explicitly set both SLC_AUX_RGN_START1 and SLC_AUX_RGN_END1 which hold MSB bits of the physical address correspondingly of region start and end otherwise SLC region operation is executed in unpredictable manner Without this patch, SLC flushes on HSDK (IOC disabled) were taking seconds. Reported-by: Vladimir Kondratiev Signed-off-by: Alexey Brodkin Signed-off-by: Vineet Gupta [vgupta: PAR40 regs only written if PAE40 exist] Signed-off-by: Greg Kroah-Hartman

ARCv2: SLC: Make sure busy bit is set properly for region ops

2017-08-30T08:26:32Z

commit b37174d95b0251611a80ef60abf03752e9d66d67 upstream. c70c473396cb "ARCv2: SLC: Make sure busy bit is set properly on SLC flushing" fixes problem for entire SLC operation where the problem was initially caught. But given a nature of the issue it is perfectly possible for busy bit to be read incorrectly even when region operation was started. So extending initial fix for regional operation as well. Signed-off-by: Alexey Brodkin Signed-off-by: Vineet Gupta Signed-off-by: Greg Kroah-Hartman

ARCv2: mm: Merge 2 updates to DC_CTRL for region flush

2017-05-02T23:16:07Z

ARCv2: mm: Implement cache region flush operations

2017-05-02T22:57:22Z

These are more efficient than the per-line ops Signed-off-by: Vineet Gupta

ARC: mm: Move full_page computation into cache version agnostic wrapper

2017-05-02T22:19:34Z

This reduces code duplication in each of cache version specific handlers Signed-off-by: Vineet Gupta

ARCv2: SLC: Make sure busy bit is set properly on SLC flushing

2017-03-31T00:32:33Z

As reported in STAR 9001165532, an SLC control reg read (for checking busy state) right after SLC invalidate command may incorrectly return NOT busy causing software to NOT spin-wait while operation is underway. (and for some reason this only happens if L1 cache is also disabled - as required by IOC programming model) Suggested workaround is to do an additional Control Reg read, which ensures the 2nd read gets the right status. Cc: stable@vger.kernel.org #4.10 Signed-off-by: Alexey Brodkin [vgupta: reworte changelog a bit] Signed-off-by: Vineet Gupta

ARC: Revert "ARC: mm: IOC: Don't enable IOC by default"

2017-01-19T03:21:06Z

The programming model has been fixed with prev patches so re-enable it by default This reverts commit 23cb1f644019bac49d87b4dd7c1eac0569cc4f53. Signed-off-by: Vineet Gupta

ARC: mm: split arc_cache_init to allow __init reaping of bulk

2017-01-19T03:21:02Z

arc_cache_init() is called for each core so can't be tagged __init. However bulk of it is only executed by master core and thus is candidate for __init reaping. So split it up to allow that. Signed-off-by: Vineet Gupta

ARCv2: IOC: Use actual memory size to setup aperture size

2017-01-18T22:52:43Z

vs. fixed 512M before. But this still assumes that all of memory is under IOC which may not be true for the SoC. Improve that later when this becomes a real issue, by specifying this from DT. Signed-off-by: Vineet Gupta