kernel.git/arch/arc/mm/cache.c, branch linux-4.10.y

ARCv2: SLC: Make sure busy bit is set properly on SLC flushing

2017-04-08T07:35:07Z

commit c70c473396cbdec1168a6eff60e13029c0916854 upstream. As reported in STAR 9001165532, an SLC control reg read (for checking busy state) right after SLC invalidate command may incorrectly return NOT busy causing software to NOT spin-wait while operation is underway. (and for some reason this only happens if L1 cache is also disabled - as required by IOC programming model) Suggested workaround is to do an additional Control Reg read, which ensures the 2nd read gets the right status. Signed-off-by: Alexey Brodkin [vgupta: reworte changelog a bit] Signed-off-by: Vineet Gupta Signed-off-by: Greg Kroah-Hartman

ARC: Revert "ARC: mm: IOC: Don't enable IOC by default"

2017-01-19T03:21:06Z

The programming model has been fixed with prev patches so re-enable it by default This reverts commit 23cb1f644019bac49d87b4dd7c1eac0569cc4f53. Signed-off-by: Vineet Gupta

ARC: mm: split arc_cache_init to allow __init reaping of bulk

2017-01-19T03:21:02Z

arc_cache_init() is called for each core so can't be tagged __init. However bulk of it is only executed by master core and thus is candidate for __init reaping. So split it up to allow that. Signed-off-by: Vineet Gupta

ARCv2: IOC: Use actual memory size to setup aperture size

2017-01-18T22:52:43Z

vs. fixed 512M before. But this still assumes that all of memory is under IOC which may not be true for the SoC. Improve that later when this becomes a real issue, by specifying this from DT. Signed-off-by: Vineet Gupta

ARCv2: IOC: Adhere to progamming model guidelines to avoid DMA corruption

2017-01-18T22:48:33Z

On AXS103 release bitfiles, DMA data corruptions were seen because IOC setup was not following the recommended way in documentation. Flipping IOC on when caches are enabled or coherency transactions are in flight, might cause some of the memory operations to not observe coherency as expected. So strictly follow the programming model recommendations as documented in comment header above arc_ioc_setup() Signed-off-by: Vineet Gupta

ARCv2: IOC: refactor the IOC and SLC operations into own functions

2017-01-18T22:35:10Z

- Move IOC setup into arc_ioc_setup() - Move SLC disabling into arc_slc_disable() Signed-off-by: Vineet Gupta

ARC: mmu: clarify the MMUv3 programming model

2017-01-05T01:12:09Z

Signed-off-by: Vineet Gupta

ARC: mm: arc700: Don't assume 2 colours for aliasing VIPT dcache

2016-12-19T19:55:17Z

An ARC700 customer reported linux boot crashes when upgrading to bigger L1 dcache (64K from 32K). Turns out they had an aliasing VIPT config and current code only assumed 2 colours, while theirs had 4. So default to 4 colours and complain if there are fewer. Ideally this needs to be a Kconfig option, but heck that's too much of hassle for a single user. Cc: stable@vger.kernel.org Signed-off-by: Vineet Gupta

ARC: mm: No need to save cache version in @cpuinfo

2016-12-19T19:54:41Z

Historical MMU revisions have been paired with Cache revision updates which are captured in MMU and Cache Build Configuration Registers respectively. This was used in boot code to check for configurations mismatches, speically in simulations (such as running with non existent caches, non pairing MMU and Cache version etc). This can instead be inferred from other cache params such as line size. So remove @ver from post processed @cpuinfo which could be used later to save soem other interesting info. Signed-off-by: Vineet Gupta

ARC: mm: IOC: Don't enable IOC by default

2016-11-28T17:18:36Z

Signed-off-by: Vineet Gupta