kernel.git/arch/arc/kernel/intc-arcv2.c, branch linux-4.17.y

ARCv2: SMP: Mask only private-per-core IRQ lines on boot at core intc

2017-08-28T23:11:15Z

Recent commit a8ec3ee861b6 "arc: Mask individual IRQ lines during core INTC init" breaks interrupt handling on ARCv2 SMP systems. That commit masked all interrupts at onset, as some controllers on some boards (customer as well as internal), would assert interrutps early before any handlers were installed. For SMP systems, the masking was done at each cpu's core-intc. Later, when the IRQ was actually requested, it was unmasked, but only on the requesting cpu. For "common" interrupts, which were wired up from the 2nd level IDU intc, this was as issue as they needed to be enabled on ALL the cpus (given that IDU IRQs are by default served Round Robin across cpus) So fix that by NOT masking "common" interrupts at core-intc, but instead at the 2nd level IDU intc (latter already being done in idu_of_init()) Fixes: a8ec3ee861b6 ("arc: Mask individual IRQ lines during core INTC init") Signed-off-by: Alexey Brodkin [vgupta: reworked changelog, removed the extraneous idu_irq_mask_raw()] Signed-off-by: Vineet Gupta Signed-off-by: Linus Torvalds

arc: Mask individual IRQ lines during core INTC init

2017-08-11T01:08:31Z

ARC cores on reset have all interrupt lines of built-in INTC enabled. Which means once we globally enable interrupts (very early on boot) faulty hardware blocks may trigger an interrupt that Linux kernel cannot handle yet as corresponding handler is not yet installed. In that case system falls in "interrupt storm" and basically never does anything useful except entering and exiting generic IRQ handling code. One real example of that kind of problematic hardware is DW GMAC which also has interrupts enabled on reset and if Ethernet PHY informs GMAC about link state, GMAC immediately reports that upstream to ARC core and here we are. Now with that change we mask all individual IRQ lines making entire system more fool-proof. [This patch was motivated by Adaptrum platform support] Signed-off-by: Alexey Brodkin Cc: Eugeniy Paltsev Tested-by: Alexandru Gagniuc Signed-off-by: Vineet Gupta

ARCv2: intc: Set default priority for all core interrupts

2017-02-06T17:37:57Z

After reset all interrupts in the core interrupt controller has the highest priority P0. If the platform supports Fast IRQs and has more than 1 banks of registers then CPU automatically switch banks of registers when P0 interrupt comes. The problem is that the kernel expects that by default switching of banks is not used by all interrupts. It is necessary to set a default nonzero priority for all available interrupts to avoid undefined behaviour. Signed-off-by: Yuriy Kolerov Signed-off-by: Vineet Gupta

ARCv2: intc: Use runtime value of irq count for setting up intc

2017-02-06T17:37:57Z

Signed-off-by: Vineet Gupta

ARC: [intc-*]: confine NR_CPU_IRQS to intc code

2017-02-06T17:37:57Z

And even this willl change in subsequent patches where we resort to using run time info instead... Signed-off-by: Vineet Gupta

ARCv2: intc: Use ARC_REG_STATUS32 for addressing STATUS32 reg

2017-02-06T17:37:57Z

It is better to use it instead of magic numbers. Signed-off-by: Yuriy Kolerov Signed-off-by: Vineet Gupta

ARC: IRQ: Use hwirq instead of virq in mask/unmask

2017-01-05T01:12:10Z

It is necessary to use hwirq instead of virq when you communicate with an interrupt controller since there is no guaranty that virq numbers match hwirq numbers. Signed-off-by: Yuriy Kolerov Signed-off-by: Vineet Gupta

ARCv2: intc: default all interrupts to priority 1

2016-12-14T17:23:46Z

ARC HS Cores support configurable multiple interrupt priorities of upto 16 levels. In commit dec2b2849cfcc ("ARCv2: intc: Allow interruption by lowest priority interrupt") we switched to 15 which seems a bit excessive given that there would be rare hardware implementing so many preemption levels AND running Linux. It would seem that 2 levels will be more common so switch to 1 as the default priority level. This will be the "lower" priority level saving 0 for implementing NMI style support. This scheme also works in systems with more than 2 prioity levels as well. Signed-off-by: Vineet Gupta

ARCv2: intc: Use kflag if STATUS32.IE must be reset

2016-09-30T21:48:24Z

In the end of "arc_init_IRQ" STATUS32.IE flag is going to be affected by "flag" instruction but "flag" never touches IE flag on ARCv2. So "kflag" instruction must be used instead of "flag". Signed-off-by: Yuriy Kolerov Cc: stable@vger.kernel.org #4.2+ Signed-off-by: Vineet Gupta

ARC: [intc-*] switch to linear domain

2016-05-09T04:02:30Z

Now that we have Timers probed from DT, don't need legacy domain This however requires mapping to be called explicitly for the IRQ which still can't (and probably never) be probed from DT such as IPI and SOFTIRQ Acked-by: Marc Zyngier Signed-off-by: Vineet Gupta