kernel.git/Documentation/devicetree/bindings/serial, branch linux-6.15.y

dt-bindings: serial: 8250: Make clocks and clock-frequency exclusive

2025-07-06T09:04:18Z

commit 09812134071b3941fb81def30b61ed36d3a5dfb5 upstream. The 8250 binding before converting to json-schema states, - clock-frequency : the input clock frequency for the UART or - clocks phandle to refer to the clk used as per Documentation/devicetree for clock-related properties, where "or" indicates these properties shouldn't exist at the same time. Additionally, the behavior of Linux's driver is strange when both clocks and clock-frequency are specified: it ignores clocks and obtains the frequency from clock-frequency, left the specified clocks unclaimed. It may even be disabled, which is undesired most of the time. But "anyOf" doesn't prevent these two properties from coexisting, as it considers the object valid as long as there's at LEAST one match. Let's switch to "oneOf" and disallows the other property if one exists, precisely matching the original binding and avoiding future confusion on the driver's behavior. Fixes: e69f5dc623f9 ("dt-bindings: serial: Convert 8250 to json-schema") Cc: stable Signed-off-by: Yao Zi Reviewed-by: Conor Dooley Link: https://lore.kernel.org/r/20250623093445.62327-1-ziyao@disroot.org Signed-off-by: Greg Kroah-Hartman

dt-bindings: serial: snps-dw-apb-uart: document RZ/N1 binding without DMA

2025-03-20T15:11:11Z

Renesas RZ/N1D has this UART with and without DMA support. Currently, only the binding with DMA support is described. Add the missing one without DMA support which can fallback even more. Signed-off-by: Wolfram Sang Reviewed-by: Miquel Raynal Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20250318085353.18990-2-wsa+renesas@sang-engineering.com Signed-off-by: Greg Kroah-Hartman

dt-bindings: serial: snps-dw-apb-uart: Add support for rk3562

2025-03-20T15:09:49Z

The UART core on Rockchip's RK3562 is the same as the one already included in generic dw-apb-uart. Extend the binding accordingly to allow compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; Signed-off-by: Kever Yang Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250227111913.2344207-9-kever.yang@rock-chips.com Signed-off-by: Greg Kroah-Hartman

dt-bindings: serial: fsl-lpuart: support i.MX94

2025-03-20T15:05:55Z

Add compatible string "fsl,imx94-lpuart" for the i.MX94 chip, which is backward compatible with i.MX8ULP. Set it to fall back to "fsl,imx8ulp-lpuart". Signed-off-by: Frank Li Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250306171052.244548-1-Frank.Li@nxp.com Signed-off-by: Greg Kroah-Hartman

dt-bindings: serial: samsung: add exynos7870-uart compatible

2025-03-20T15:05:33Z

Document the compatible string for Exynos7870's UART driver. The devicetree property samsung,uart-fifosize must be mandatory, as the driver enquires about the FIFO sizes. This feature makes it compatible with Exynos8895's UART. Signed-off-by: Kaustabh Chakraborty Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250219-exynos7870-uart-v2-1-c8c67f3a936c@disroot.org Signed-off-by: Greg Kroah-Hartman

dt-bindings: serial: Add bindings for nvidia,tegra264-utc

2025-02-14T09:06:50Z

The Tegra UTC (UART Trace Controller) allows multiple clients within the Tegra SoC to share a physical UART interface. It supports up to 16 clients. Each client operates as an independent UART endpoint with a dedicated interrupt and 128-character TX/RX FIFOs. Add device tree binding documentation for the Tegra UTC client. Signed-off-by: Kartik Rajput Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250213125612.4705-2-kkartik@nvidia.com Signed-off-by: Greg Kroah-Hartman

dt-bindings: serial: Allow fsl,ns16550 with broken FIFOs

2025-02-14T09:05:21Z

While testing on a Freescale MPC8314E board, I noticed that changing the UART compatible string from ns16550 to ns16550a breaks the output, suggesting that the FIFOs don't work correctly. To accommodate this fact, move the definition of fsl,ns16550 to the section of 8250.yaml that allows broken FIFOs. Signed-off-by: J. Neuschäfer Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250209-uartfifo-v1-1-501a510a5f07@posteo.net Signed-off-by: Greg Kroah-Hartman

Revert "dt-bindings: serial: 8250: Add Airoha compatibles"

2025-02-06T05:16:32Z

This reverts commit ed333392bd201e71a010e588e61605a1e2dd07df. It was part of a patch series that caused build errors in linux-next. Cc: Benjamin Larsson Reported-by: Stephen Rothwell Link: https://lore.kernel.org/r/20250206135328.4bad1401@canb.auug.org.au Signed-off-by: Greg Kroah-Hartman

dt-bindings: serial: pl011: Add optional power-domains property

2025-02-04T13:39:48Z

AMD/Xilinx Versal device serial IP has its own power domain, so add an optional property to describe it. Signed-off-by: Manikanta Guntupalli Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250129095013.2145580-1-manikanta.guntupalli@amd.com Signed-off-by: Greg Kroah-Hartman

dt-bindings: serial: 8250: Add Airoha compatibles

2025-02-04T13:39:20Z

The Airoha SoC family have a mostly 16550-compatible UART and High-Speed UART hardware with the exception of custom baud rate settings register. Signed-off-by: Benjamin Larsson Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250119130105.2833517-2-benjamin.larsson@genexis.eu Signed-off-by: Greg Kroah-Hartman