<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/Documentation/devicetree/bindings/pci, branch linux-6.4.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-6.4.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-6.4.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2023-05-09T06:01:49Z</updated>
<entry>
<title>dt-bindings: PCI: fsl,imx6q: fix assigned-clocks warning</title>
<updated>2023-05-09T06:01:49Z</updated>
<author>
<name>Krzysztof Kozlowski</name>
</author>
<published>2023-05-08T07:18:37Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=8bbec86ce6d66fb33530c679f7bb3a123fc9e7da'/>
<id>urn:sha1:8bbec86ce6d66fb33530c679f7bb3a123fc9e7da</id>
<content type='text'>
assigned-clocks are a dependency of clocks, however the dtschema has
limitation and expects clocks to be present in the binding using
assigned-clocks, not in other referenced bindings.  The clocks were
defined in common fsl,imx6q-pcie-common.yaml, which is referenced by
fsl,imx6q-pcie-ep.yaml.  The fsl,imx6q-pcie-ep.yaml used assigned-clocks
thus leading to warnings:

  Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.example.dtb: pcie-ep@33800000:
    Unevaluated properties are not allowed ('assigned-clock-parents', 'assigned-clock-rates', 'assigned-clocks' were unexpected)
  From schema: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml

Fix this by moving clocks to each specific schema from the common one
and narrowing them to strictly match what is expected for given device.

Fixes: b10f82380eeb ("dt-bindings: imx6q-pcie: Restruct i.MX PCIe schema")
Acked-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Reviewed-by: Richard Zhu &lt;hongxing.zhu@nxp.com&gt;
Link: https://lore.kernel.org/r/20230508071837.68552-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'phy-for-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy</title>
<updated>2023-05-03T18:17:34Z</updated>
<author>
<name>Linus Torvalds</name>
</author>
<published>2023-05-03T18:17:34Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=54bdf8a39931cf8fe2c74432e715353d9a1c1107'/>
<id>urn:sha1:54bdf8a39931cf8fe2c74432e715353d9a1c1107</id>
<content type='text'>
Pull phy updates from Vinod Koul:
 "New support:
   - UFS PHY for Qualcomm SA8775p, SM7150
   - PCIe 2 lane phy support for sc8180x and PCIe PHY for SDX65
   - Mediatke hdmi phy support for mt8195
   - rockchip naneng combo phy support for RK358

  Updates:
   - Drop Thunder Bay eMMC PHY driver
   - RC support for PCIe phy for Qualcomm SDX55
   - SGMII support in WIZ driver for J721E
   - PCIe and multilink SGMII PHY support in cadence driver
   - Big pile of platform remove callback returning void conversions"

* tag 'phy-for-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (77 commits)
  phy: cadence: cdns-dphy-rx: Add common module reset support
  phy: ti: j721e-wiz: Add SGMII support in WIZ driver for J721E
  dt-bindings: phy: ti: phy-gmii-sel: Add support for J784S4 CPSW9G
  phy: ti: j721e-wiz: Fix unreachable code in wiz_mode_select()
  phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configuration
  phy: mediatek: add support for phy-mtk-hdmi-mt8195
  phy: phy-mtk-hdmi: Add generic phy configure callback
  dt-bindings: phy: mediatek: hdmi-phy: Add mt8195 compatible
  phy: tegra: xusb: Add missing tegra_xusb_port_unregister for usb2_port and ulpi_port
  dt-bindings: phy: ti,phy-j721e-wiz: document clock-output-names
  dt-bindings: phy: ti,phy-j721e-wiz: drop assigned-clocks
  dt-bindings: phy: ti,phy-am654-serdes: drop assigned-clocks type
  dt-bindings: phy: cadence-torrent: drop assigned-clocks
  dt-bindings: phy: cadence-sierra: drop assigned-clocks
  phy: rockchip: remove unused hw_to_inno function
  phy: qualcomm: phy-qcom-qmp-ufs: add definitions for sa8775p
  dt-bindings: phy: qmp-ufs: describe the UFS PHY for sa8775p
  phy: qcom-qmp-pcie: drop sdm845_qhp_pcie_rx_tbl
  phy: qcom-qmp-pcie: sc8180x PCIe PHY has 2 lanes
  phy: qcom-qmp-ufs: Add SM7150 support
  ...
</content>
</entry>
<entry>
<title>Merge tag 'pci-v6.4-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci</title>
<updated>2023-04-27T17:45:30Z</updated>
<author>
<name>Linus Torvalds</name>
</author>
<published>2023-04-27T17:45:30Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=34b62f186db9614e55d021f8c58d22fc44c57911'/>
<id>urn:sha1:34b62f186db9614e55d021f8c58d22fc44c57911</id>
<content type='text'>
Pull pci updates from Bjorn Helgaas:
 "Resource management:

   - Add pci_dev_for_each_resource() and pci_bus_for_each_resource()
     iterators

  PCIe native device hotplug:

   - Fix AB-BA deadlock between reset_lock and device_lock

  Power management:

   - Wait longer for devices to become ready after resume (as we do for
     reset) to accommodate Intel Titan Ridge xHCI devices

   - Extend D3hot delay for NVIDIA HDA controllers to avoid
     unrecoverable devices after a bus reset

  Error handling:

   - Clear PCIe Device Status after EDR since generic error recovery now
     only clears it when AER is native

  ASPM:

   - Work around Chromebook firmware defect that clobbers Capability
     list (including ASPM L1 PM Substates Cap) when returning from
     D3cold to D0

  Freescale i.MX6 PCIe controller driver:

   - Install imprecise external abort handler only when DT indicates
     PCIe support

  Freescale Layerscape PCIe controller driver:

   - Add ls1028a endpoint mode support

  Qualcomm PCIe controller driver:

   - Add SM8550 DT binding and driver support

   - Add SDX55 DT binding and driver support

   - Use bulk APIs for clocks of IP 1.0.0, 2.3.2, 2.3.3

   - Use bulk APIs for reset of IP 2.1.0, 2.3.3, 2.4.0

   - Add DT "mhi" register region for supported SoCs

   - Expose link transition counts via debugfs to help debug low power
     issues

   - Support system suspend and resume; reduce interconnect bandwidth
     and turn off clock and PHY if there are no active devices

   - Enable async probe by default to reduce boot time

  Miscellaneous:

   - Sort controller Kconfig entries by vendor"

* tag 'pci-v6.4-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (56 commits)
  PCI: xilinx: Drop obsolete dependency on COMPILE_TEST
  PCI: mobiveil: Sort Kconfig entries by vendor
  PCI: dwc: Sort Kconfig entries by vendor
  PCI: Sort controller Kconfig entries by vendor
  PCI: Use consistent controller Kconfig menu entry language
  PCI: xilinx-nwl: Add 'Xilinx' to Kconfig prompt
  PCI: hv: Add 'Microsoft' to Kconfig prompt
  PCI: meson: Add 'Amlogic' to Kconfig prompt
  PCI: Use of_property_present() for testing DT property presence
  PCI/PM: Extend D3hot delay for NVIDIA HDA controllers
  dt-bindings: PCI: qcom: Document msi-map and msi-map-mask properties
  PCI: qcom: Add SM8550 PCIe support
  dt-bindings: PCI: qcom: Add SM8550 compatible
  PCI: qcom: Add support for SDX55 SoC
  dt-bindings: PCI: qcom-ep: Fix the unit address used in example
  dt-bindings: PCI: qcom: Add SDX55 SoC
  dt-bindings: PCI: qcom: Update maintainers entry
  PCI: qcom: Enable async probe by default
  PCI: qcom: Add support for system suspend and resume
  PCI/PM: Drop pci_bridge_wait_for_secondary_bus() timeout parameter
  ...
</content>
</entry>
<entry>
<title>Merge tag 'devicetree-for-6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux</title>
<updated>2023-04-27T16:23:57Z</updated>
<author>
<name>Linus Torvalds</name>
</author>
<published>2023-04-27T16:23:57Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=d42b1c47570eb2ed818dc3fe94b2678124af109d'/>
<id>urn:sha1:d42b1c47570eb2ed818dc3fe94b2678124af109d</id>
<content type='text'>
Pull devicetree updates from Rob Herring:
 "Bindings:

   - Convert Qcom IOMMU, Amlogic timer, Freescale sec-v4.0, Toshiba
     TC358764 display bridge, Parade PS8622 display bridge, and Xilinx
     FPGA bindings to DT schema format

   - Add qdu1000 and sa8775p SoC support to Qcom PDC interrupt
     controller

   - Add MediaTek MT8365 UART and SYSIRQ bindings

   - Add Arm Cortex-A78C and X1C core compatibles

   - Add vendor prefix for Novatek

   - Remove bindings for stih415, sti416, stid127 platforms

   - Drop uneeded quotes in schema files. This is preparation for
     yamllint checking quoting for us.

   - Add missing (unevaluated|additional)Properties constraints on child
     node schemas

   - Clean-up schema comments formatting

   - Fix I2C and SPI node bus names in schema examples

   - Clean-up some display compatibles schema syntax

   - Fix incorrect references to lvds.yaml

   - Gather all cache controller bindings in a common directory

  DT core:

   - Convert unittest to new void .remove platform device hook

   - kerneldoc fixes for DT address of_pci_range_to_resource/
     of_address_to_resource functions"

* tag 'devicetree-for-6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (46 commits)
  dt-bindings: rng: Drop unneeded quotes
  dt-bindings: arm/soc: mediatek: Drop unneeded quotes
  dt-bindings: soc: qcom: Drop unneeded quotes
  dt-bindings: i2c: samsung: Fix 'deprecated' value
  dt-bindings: display: Fix lvds.yaml references
  dt-bindings: display: simplify compatibles syntax
  dt-bindings: display: mediatek: simplify compatibles syntax
  dt-bindings: drm/bridge: ti-sn65dsi86: Fix the video-interfaces.yaml references
  dt-bindings: timer: Drop unneeded quotes
  dt-bindings: interrupt-controller: qcom,pdc: document qcom,qdu1000-pdc
  dt-bindings: interrupt-controller: qcom-pdc: add compatible for sa8775p
  dt-bindings: reset: remove stih415/stih416 reset
  dt-bindings: net: dwmac: sti: remove stih415/sti416/stid127
  dt-bindings: irqchip: sti: remove stih415/stih416 and stid127
  dt-bindings: iommu: Convert QCOM IOMMU to YAML
  dt-bindings: irqchip: ti,sci-inta: Add optional power-domains property
  dt-bindings: Add missing (unevaluated|additional)Properties on child node schemas
  of: address: Reshuffle to remove forward declarations
  of: address: Fix documented return value of of_pci_range_to_resource()
  of: address: Document return value of of_address_to_resource()
  ...
</content>
</entry>
<entry>
<title>Merge branch 'pci/controller/qcom'</title>
<updated>2023-04-20T21:16:38Z</updated>
<author>
<name>Bjorn Helgaas</name>
</author>
<published>2023-04-20T21:16:38Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=5c5dd8839fc02fa9b9558005a32ce4d7d86fd774'/>
<id>urn:sha1:5c5dd8839fc02fa9b9558005a32ce4d7d86fd774</id>
<content type='text'>
- Use correct PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 register for v2.7.0
  (Manivannan Sadhasivam)

- Remove "PCIE20_" prefix from register definitions (Manivannan Sadhasivam)

- Sort registers and bitfield declarations (Manivannan Sadhasivam)

- Convert to GENMASK and FIELD_PREP (Manivannan Sadhasivam)

- Use bulk APIs for clocks of IP 1.0.0, 2.3.2, 2.3.3 (Manivannan
  Sadhasivam)

- Use bulk APIs for reset of IP 2.1.0, 2.3.3, 2.4.0 (Manivannan Sadhasivam)

- Rename qcom_pcie_config_sid_sm8250() to be non SM8250-specific
  (Manivannan Sadhasivam)

- Add DT "mhi" register region for supported SoCs (Manivannan Sadhasivam)

- Expose link transition counts via debugfs to help debug low power issues
  (Manivannan Sadhasivam)

- Support system suspend and resume; reduce interconnect bandwidth and turn
  off clock and PHY if there are no active devices (Manivannan Sadhasivam)

- Enable async probe by default to reduce boot time (Manivannan Sadhasivam)

- Add Manivannan Sadhasivam as qcom DT binding maintainer, replacing
  Stanimir Varbanov (Manivannan Sadhasivam)

- Add DT binding and driver support for Qcom SDX55 SoC (Manivannan
  Sadhasivam)

- Add DT binding and driver support for SM8550 SoC (Abel Vesa)

- Document msi-map and msi-map-mask DT properties (Manivannan Sadhasivam)

* pci/controller/qcom:
  dt-bindings: PCI: qcom: Document msi-map and msi-map-mask properties
  PCI: qcom: Add SM8550 PCIe support
  dt-bindings: PCI: qcom: Add SM8550 compatible
  PCI: qcom: Add support for SDX55 SoC
  dt-bindings: PCI: qcom-ep: Fix the unit address used in example
  dt-bindings: PCI: qcom: Add SDX55 SoC
  dt-bindings: PCI: qcom: Update maintainers entry
  PCI: qcom: Enable async probe by default
  PCI: qcom: Add support for system suspend and resume
  PCI: qcom: Expose link transition counts via debugfs
  dt-bindings: PCI: qcom: Add "mhi" register region to supported SoCs
  PCI: qcom: Rename qcom_pcie_config_sid_sm8250() to reflect IP version
  PCI: qcom: Use macros for defining total no. of clocks &amp; supplies
  PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.4.0
  PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.3.3
  PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.3
  PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.2
  PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 1.0.0
  PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.1.0
  PCI: qcom: Use lower case for hex
  PCI: qcom: Add missing macros for register fields
  PCI: qcom: Use bitfield definitions for register fields
  PCI: qcom: Sort and group registers and bitfield definitions
  PCI: qcom: Remove PCIE20_ prefix from register definitions
  PCI: qcom: Fix the incorrect register usage in v2.7.0 config
</content>
</entry>
<entry>
<title>dt-bindings: PCI: qcom: Document msi-map and msi-map-mask properties</title>
<updated>2023-04-12T13:22:32Z</updated>
<author>
<name>Manivannan Sadhasivam</name>
</author>
<published>2023-04-11T12:14:42Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=c025c7e5dbf4706279183c16788fa83001b8331e'/>
<id>urn:sha1:c025c7e5dbf4706279183c16788fa83001b8331e</id>
<content type='text'>
The Qcom PCIe controller is capable of using either internal MSI controller
or the external GIC-ITS for signaling MSIs sent by endpoint devices.
Currently, the binding only documents the internal MSI implementation.

Let's document the GIC-ITS imeplementation by making use of msi-map and
msi-map-mask properties. Only one of the implementation should be used
at a time and the drivers can choose the preferred one.

Link: https://lore.kernel.org/r/20230411121442.22227-1-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam &lt;manivannan.sadhasivam@linaro.org&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lpieralisi@kernel.org&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: PCI: qcom: Add SM8550 compatible</title>
<updated>2023-04-12T13:22:25Z</updated>
<author>
<name>Abel Vesa</name>
</author>
<published>2023-03-20T14:46:57Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=1a24edc38dbfa9e77461b5e2bb84441351181574'/>
<id>urn:sha1:1a24edc38dbfa9e77461b5e2bb84441351181574</id>
<content type='text'>
Add the SM8550 platform to the binding.

Link: https://lore.kernel.org/r/20230320144658.1794991-1-abel.vesa@linaro.org
Signed-off-by: Abel Vesa &lt;abel.vesa@linaro.org&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lpieralisi@kernel.org&gt;
Reviewed-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Reviewed-by: Johan Hovold &lt;johan+linaro@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: PCI: qcom-ep: Fix the unit address used in example</title>
<updated>2023-04-12T08:11:02Z</updated>
<author>
<name>Manivannan Sadhasivam</name>
</author>
<published>2023-03-08T08:24:15Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=e12b6893d2333f08dc108ab045b7744adc198bed'/>
<id>urn:sha1:e12b6893d2333f08dc108ab045b7744adc198bed</id>
<content type='text'>
Unit address of PCIe EP node should be 0x1c00000 as it has to match the
first address specified in the reg property.

Link: https://lore.kernel.org/r/20230308082424.140224-5-manivannan.sadhasivam@linaro.org
Fixes: 31c9ef002580 ("dt-bindings: PCI: Add Qualcomm PCIe Endpoint controller")
Signed-off-by: Manivannan Sadhasivam &lt;manivannan.sadhasivam@linaro.org&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lpieralisi@kernel.org&gt;
Reviewed-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: PCI: qcom: Add SDX55 SoC</title>
<updated>2023-04-12T08:11:02Z</updated>
<author>
<name>Manivannan Sadhasivam</name>
</author>
<published>2023-03-08T08:24:14Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=1bc7ae328cedd5fefbda443c70c304fa66963437'/>
<id>urn:sha1:1bc7ae328cedd5fefbda443c70c304fa66963437</id>
<content type='text'>
Add support for the PCIe controller on the Qcom SDX55 SoC to the binding.

Link: https://lore.kernel.org/r/20230308082424.140224-4-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam &lt;manivannan.sadhasivam@linaro.org&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lpieralisi@kernel.org&gt;
Reviewed-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: PCI: qcom: Update maintainers entry</title>
<updated>2023-04-12T06:49:04Z</updated>
<author>
<name>Manivannan Sadhasivam</name>
</author>
<published>2023-03-08T08:24:12Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=a4c716706f3f1725ebf578d9c8db63b36b9570e1'/>
<id>urn:sha1:a4c716706f3f1725ebf578d9c8db63b36b9570e1</id>
<content type='text'>
Stan is no longer working with MMSOL and expressed his interest to not
continue maintaining Qcom PCIe driver. Since I took over the driver
maintainership, I'm stepping in to maintain the binding also.

Link: https://lore.kernel.org/r/20230308082424.140224-2-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam &lt;manivannan.sadhasivam@linaro.org&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lpieralisi@kernel.org&gt;
Acked-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
</content>
</entry>
</feed>
