kernel.git/Documentation/devicetree/bindings/mmc, branch linux-4.0.y

Merge tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux

2015-02-21T20:30:30Z

Pull clock framework updates from Mike Turquette: "The clock framework changes contain the usual driver additions, enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based devices. Additionally the framework core underwent a bit of surgery with two major changes: - The boundary between the clock core and clock providers (e.g clock drivers) is now more well defined with dedicated provider helper functions. struct clk no longer maps 1:1 with the hardware clock but is a true per-user cookie which helps us tracker users of hardware clocks and debug bad behavior. - The addition of rate constraints for clocks. Rate ranges are now supported which are analogous to the voltage ranges in the regulator framework. Unfortunately these changes to the core created some breakeage. We think we fixed it all up but for this reason there are lots of last minute commits trying to undo the damage" * tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux: (113 commits) clk: Only recalculate the rate if needed Revert "clk: mxs: Fix invalid 32-bit access to frac registers" clk: qoriq: Add support for the platform PLL powerpc/corenet: Enable CLK_QORIQ clk: Replace explicit clk assignment with __clk_hw_set_clk clk: Add __clk_hw_set_clk helper function clk: Don't dereference parent clock if is NULL MIPS: Alchemy: Remove bogus args from alchemy_clk_fgcs_detr clkdev: Always allocate a struct clk and call __clk_get() w/ CCF clk: shmobile: div6: Avoid division by zero in .round_rate() clk: mxs: Fix invalid 32-bit access to frac registers clk: omap: compile legacy omap3 clocks conditionally clkdev: Export clk_register_clkdev clk: Add rate constraints to clocks clk: remove clk-private.h pci: xgene: do not use clk-private.h arm: omap2+ remove dead clock code clk: Make clk API return per-user struct clk instances clk: tegra: Define PLLD_DSI and remove dsia(b)_mux clk: tegra: Add support for the Tegra132 CAR IP block ...

Merge tag 'devicetree-for-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

2015-02-12T16:58:43Z

Pull DeviceTree changes from Rob Herring: - DT unittests for I2C probing and overlays from Pantelis Antoniou - Remove DT unittest dependency on OF_DYNAMIC from Gaurav Minocha - Add Tegra compatible strings missing for newer parts from Paul Walmsley - Various vendor prefix additions * tag 'devicetree-for-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: of: Add vendor prefix for OmniVision Technologies of: Use ovti for Omnivision of: Add vendor prefix for Truly Semiconductors Limited of: Add vendor prefix for Himax Technologies Inc. of/fdt: fix sparse warning of: unitest: Add I2C overlay unit tests. Documentation: DT: document compatible string existence requirement Documentation: DT bindings: add nvidia, tegra132-denver compatible string Documentation: DT bindings: add more Tegra chip compatible strings of: EXPORT_SYMBOL_GPL of_property_read_u64_array of: Fix brace position for struct of_device_id definition of/unittest: Remove obsolete code dt-bindings: use isil prefix for Intersil in vendor-prefixes.txt Add AD Holdings Plc. to vendor-prefixes. dt-bindings: Add Silicon Mitus vendor prefix Removes OF_UNITTEST dependency on OF_DYNAMIC config symbol pinctrl: fix up device tree bindings DT: Vendors: Add Everspin doc: add bindings document for altera fpga manager drivers: of: Export of_reserved_mem_device_{init,release}

mmc: pwrseq: add driver for emmc hardware reset

2015-02-04T08:45:09Z

This patch provides a simple mmc-pwrseq-emmc driver, which controls single gpio line. It perform standard eMMC hw reset procedure, as descibed by Jedec 4.4 specification. This procedure is performed just after MMC core enabled power to the given mmc host (to fix possible issues if bootloader has left eMMC card in initialized or unknown state), and before performing complete system reboot (also in case of emergency reboot call). The latter is needed on boards, which doesn't have hardware reset logic connected to emmc card and (limited or broken) ROM bootloaders are unable to read second stage from the emmc card if the card is left in unknown or already initialized state. Signed-off-by: Marek Szyprowski Signed-off-by: Ulf Hansson

Documentation: DT bindings: add more Tegra chip compatible strings

2015-02-04T02:37:31Z

Align compatible strings for several IP blocks present on Tegra chips with the latest doctrine from the DT maintainers: http://marc.info/?l=devicetree&m=142255654213019&w=2 The primary objective here is to avoid checkpatch warnings, per: http://marc.info/?l=linux-tegra&m=142201349727836&w=2 DT binding text files have been updated for the following IP blocks: - PCIe - SOR - SoC timers - AHB "gizmo" - APB_MISC - pinmux control - UART - PWM - I2C - SPI - RTC - PMC - eFuse - AHCI - HDA - XUSB_PADCTRL - SDHCI - SOC_THERM - AHUB - I2S - EHCI - USB PHY N.B. The nvidia,tegra20-timer compatible string is removed from the nvidia,tegra30-timer.txt documentation file because it's already mentioned in the nvidia,tegra20-timer.txt documentation file. This second version takes into account the following requests from Rob Herring : - Per-IP block patches have been combined into a single patch - Explicit documentation about which compatible strings are actually matched by the driver has been removed. In its place is implicit documentation that loosely follows Rob's prescribed format: "Must contain '"nvidia,-pcie", "nvidia,tegra20-pcie"' where is tegra30, tegra132, ..." [...] "You should attempt to document known values of if you use it" Signed-off-by: Paul Walmsley Cc: Alexandre Courbot Cc: Dylan Reid Cc: Greg Kroah-Hartman Cc: Hans de Goede Cc: Ian Campbell Cc: Jingchang Lu Cc: John Crispin Cc: Kumar Gala Cc: Linus Walleij Cc: Mark Rutland Cc: Mikko Perttunen Cc: Murali Karicheri Cc: Paul Walmsley Cc: Pawel Moll Cc: Peter De Schrijver Cc: Peter Hurley Cc: Sean Paul Cc: Stephen Warren Cc: Takashi Iwai Cc: Tejun Heo Cc: "Terje Bergström" Cc: Thierry Reding Cc: Tuomas Tynkkynen Cc: Wolfram Sang Cc: Zhang Rui Cc: dri-devel@lists.freedesktop.org Cc: linux-i2c@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-pwm@vger.kernel.org Cc: linux-tegra@vger.kernel.org Acked-by: Eduardo Valentin Signed-off-by: Rob Herring

mmc: pwrseq: Document optional clock for the simple power sequence

2015-01-30T11:03:16Z

Some WLAN chips attached to a SDIO interface, need an external clock to be operational. Since this is very common, extend the simple MMC power sequence DT binding to support an optional clock. Signed-off-by: Javier Martinez Canillas Signed-off-by: Ulf Hansson

mmc: pwrseq: Document that simple sequence support more than one GPIO

2015-01-30T10:59:38Z

Many SDIO/MMC attached WLAN chips need more than one ping for their reset sequence. Extend the pwrseq_simple binding to support more than one pin. Signed-off-by: Javier Martinez Canillas Signed-off-by: Ulf Hansson

mmc: sdhci-pxav3: Extend binding with SDIO3 conf reg for the Armada 38x

2015-01-29T12:08:22Z

The SDHCI unit used on the Armada 38x needs using an extra register to do specific clock adjustments in order to support the SDR50 and DDR50 modes. This patch extends the binding to allow using this register. Signed-off-by: Gregory CLEMENT Signed-off-by: Ulf Hansson

mmc: pwrseq: Document DT bindings for the simple MMC power sequence

2015-01-28T11:32:01Z

To support SOCs which specifies specific MMC power sequences, document some MMC DT bindings to be able to describe these hardwares. Let's also document bindings for a simple MMC power sequence provider, which purpose is to support a set of common properties between various SOCs. In this initial step, let's also document a top level description of the MMC power sequence and describe the compatible string used for the simple MMC power sequence provider. The simple MMC power sequence provider will initially support a reset GPIO. From several earlier posted patches, it's clear that such hardware exists. Especially some WLAN chips which are attached to an SDIO interface may use a GPIO reset. Signed-off-by: Ulf Hansson Tested-by: Javier Martinez Canillas Reviewed-by: Javier Martinez Canillas

mmc: sdhci: host: add new f_sdh30

2015-01-20T08:32:37Z

This patch adds new host controller driver for Fujitsu SDHCI controller f_sdh30. Signed-off-by: Vincent Yang Signed-off-by: Andy Green Signed-off-by: Tetsuya Takinishi Signed-off-by: Ulf Hansson

mmc: Add SDIO function subnode DT documentation

2015-01-19T08:56:26Z

While SDIO devices are runtime probable they sometimes need nonprobable additional information on embedded systems, like an additional gpio interrupt or a clock. This binding describes how to add child nodes to the devicetree to supply this information. Signed-off-by: Sascha Hauer [hdegoede@redhat.com: Documented the need for #address- and #size-cells] [hdegoede@redhat.com: Added a real world example] Signed-off-by: Hans de Goede Signed-off-by: Ulf Hansson