kernel.git/Documentation/devicetree/bindings/gpio, branch linux-6.15.y

dt-bindings: xilinx: Remove myself from maintainership

2025-04-07T14:34:35Z

As I am leaving AMD and will no longer be maintaining these platform drivers, so removing myself from maintainership. Signed-off-by: Mubin Sayyed Acked-by: Damien Le Moal Acked-by: Bartosz Golaszewski Link: https://lore.kernel.org/r/20250403060836.2602361-1-mubin.sayyed@amd.com Signed-off-by: Rob Herring (Arm)

dt-bindings: gpio: vf610: Add i.MX94 support

2025-03-10T10:20:38Z

Add compatible string "fsl,imx94-gpio" for the i.MX94 chip, which is backward compatible with i.MX8ULP. Set it to fall back to "fsl,imx8ulp-gpio". Signed-off-by: Frank Li Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250306170921.241690-1-Frank.Li@nxp.com Signed-off-by: Bartosz Golaszewski

dt-bindings: gpio: loongson: Add new loongson gpio chip compatible

2025-03-05T08:55:56Z

Add the devicetree compatibles for Loongson-7A2000 and Loongson-3A6000 gpio chip. Signed-off-by: Binbin Zhou Acked-by: Rob Herring (Arm) Reviewed-by: Linus Walleij Acked-by: Huacai Chen Link: https://lore.kernel.org/r/20250303074552.3335186-1-zhoubinbin@loongson.cn Signed-off-by: Bartosz Golaszewski

dt-bindings: gpio: mvebu: Add missing 'gpio-ranges' property and hog nodes

2025-03-04T10:39:34Z

The Marvell mvebu binding users already use 'gpio-ranges' and have hog nodes, so add them to the binding. Signed-off-by: Rob Herring (Arm) Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20250227175132.3734524-1-robh@kernel.org Signed-off-by: Bartosz Golaszewski

dt-bindings: gpio: nxp,pcf8575: add reset GPIO

2025-02-26T10:25:30Z

A few of the I2C GPIO expander chips supported by this binding have a RESETN pin to be able to reset the chip. The chip is held in reset while the pin is low, therefore the polarity of reset-gpios is expected to reflect that, i.e. a GPIO_ACTIVE_HIGH means the GPIO will be driven high for reset and then driven low, GPIO_ACTIVE_LOW means the GPIO will be driven low for reset and then driven high. If a GPIO is directly routed to RESETN pin on the IC without any inverter, GPIO_ACTIVE_LOW is thus expected. Out of the supported chips, only PCA9670, PCA9671, PCA9672 and PCA9673 show a RESETN pin in their datasheets. They all share the same reset timings, that is 4+us reset pulse[0] and 100+us reset time[0]. When performing a reset, "The PCA9670 registers and I2C-bus state machine will be held in their default state until the RESET input is once again HIGH."[1] meaning we now know the state of each line controlled by the GPIO expander. Therefore, setting lines-initial-states and reset-gpios both does not make sense and their presence is XOR'ed. [0] https://www.nxp.com/docs/en/data-sheet/PCA9670.pdf Fig 22. [1] https://www.nxp.com/docs/en/data-sheet/PCA9670.pdf 8.5 Tested-by: Heiko Stuebner # exclusion logic Acked-by: Conor Dooley Reviewed-by: Laurent Pinchart Signed-off-by: Quentin Schulz Link: https://lore.kernel.org/r/20250224-pca976x-reset-driver-v3-1-58370ef405be@cherry.de Signed-off-by: Bartosz Golaszewski

dt-bindings: gpio: ast2400-gpio: Add hogs parsing

2025-02-05T08:39:57Z

Allow parsing GPIO controller children nodes with GPIO hogs. Reviewed-by: Rob Herring (Arm) Signed-off-by: Ninad Palsule Link: https://lore.kernel.org/r/20250204194115.3899174-3-ninad@linux.ibm.com Signed-off-by: Bartosz Golaszewski

dt-bindings: gpio: fsl,qoriq-gpio: Add compatible string fsl,mpc8314-gpio

2025-01-13T08:20:25Z

This is for the MPC831{4,5}{,E} SoCs. Signed-off-by: J. Neuschäfer Reviewed-by: Linus Walleij Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250102-mpc83xx-v1-11-86f78ba2a7af@posteo.net Signed-off-by: Bartosz Golaszewski

dt-bindings: gpio: fairchild,74hc595: Document chip select vs. latch clock

2025-01-13T08:20:25Z

From looking at the data sheets, it is not obvious that CS# and latch clock can be treated at the same, but doing so works fine and saves the hassle of (1) trying to specify a SPI device without CS, and (2) adding another property to drive the latch clock[1]. [1]: https://lore.kernel.org/lkml/20241213-gpio74-v1-2-fa2c089caf41@posteo.net/ Signed-off-by: J. Neuschäfer Reviewed-by: Linus Walleij Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20241224-gpio74-v2-3-bbcf14183191@posteo.net Signed-off-by: Bartosz Golaszewski

dt-bindings: gpio: brcmstb: permit gpio-line-names property

2024-12-16T09:08:19Z

gpio-line-names is a generic property that can be supported by any GPIO controller, so permit it through the binding. It is permitted to have a variable number of GPIOs per node based on brcm,gpio-bank-widths, so define an arbitrary maximum number of items based on current users. Signed-off-by: Dave Stevenson Acked-by: Florian Fainelli Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20241212-dt-bcm2712-fixes-v3-3-44a7f3390331@raspberrypi.com Signed-off-by: Bartosz Golaszewski

dt-bindings: gpio-mmio: Add ngpios property

2024-10-18T07:45:33Z

This adds the ngpios property to MMIO GPIO. We restrict the property to 1..63 since there is no point in 0 GPIO lines and we support up to 64bits wide registers for now. Acked-by: Rob Herring (Arm) Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20241017-gpio-ngpios-v2-1-cecfdb38d40e@linaro.org Signed-off-by: Bartosz Golaszewski