<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/Documentation/devicetree/bindings/display/tegra, branch master</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=master</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=master'/>
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<updated>2026-01-17T00:31:19Z</updated>
<entry>
<title>dt-bindings: display: tegra: document Tegra30 VI and VIP</title>
<updated>2026-01-17T00:31:19Z</updated>
<author>
<name>Svyatoslav Ryhel</name>
</author>
<published>2025-10-22T14:20:32Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=d262d030baef287da33344a932639aab5f913c3a'/>
<id>urn:sha1:d262d030baef287da33344a932639aab5f913c3a</id>
<content type='text'>
Existing Parallel VI interface schema for Tegra20 is fully compatible with
Tegra30; hence, lets reuse it by setting fallback for Tegra30.

Adjust existing VI schema to reflect that Tegra20 VI is compatible with
Tegra30 by setting a fallback for Tegra30. Additionally, switch to using
an enum instead of list of const.

Signed-off-by: Svyatoslav Ryhel &lt;clamor95@gmail.com&gt;
Reviewed-by: Rob Herring (Arm) &lt;robh@kernel.org&gt;
Tested-by: Luca Ceresoli &lt;luca.ceresoli@bootlin.com&gt; # tegra20, parallel camera
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: display: tegra: document Tegra132 MIPI calibration device</title>
<updated>2026-01-17T00:23:30Z</updated>
<author>
<name>Svyatoslav Ryhel</name>
</author>
<published>2025-10-22T14:20:38Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=d6e8b796d0d67699c74ee3cbc46601cf9ec925bb'/>
<id>urn:sha1:d6e8b796d0d67699c74ee3cbc46601cf9ec925bb</id>
<content type='text'>
Document MIPI calibration device found in Tegra132. This compatible
already exists in the Linux kernel, I have just documented it to satisfy
warnings.

Each Tegra SoC generation has unique set of registers which should be
configured. They all differ, hence fallback is not suitable here.

Signed-off-by: Svyatoslav Ryhel &lt;clamor95@gmail.com&gt;
Acked-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Tested-by: Luca Ceresoli &lt;luca.ceresoli@bootlin.com&gt; # tegra20, parallel camera
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: display: tegra: Document Tegra20 and Tegra30 CSI</title>
<updated>2025-11-14T14:54:57Z</updated>
<author>
<name>Svyatoslav Ryhel</name>
</author>
<published>2025-10-22T14:49:28Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=e7dc9c3a6fc46e2530119b7c1d174fa9af2b6acb'/>
<id>urn:sha1:e7dc9c3a6fc46e2530119b7c1d174fa9af2b6acb</id>
<content type='text'>
Document CSI HW block found in Tegra20 and Tegra30 SoC.

The #nvidia,mipi-calibrate-cells is not an introduction of property, such
property already exists in nvidia,tegra114-mipi.yaml and is used in
multiple device trees. In case of Tegra30 and Tegra20 CSI block combines
mipi calibration function and CSI function, in Tegra114+ mipi calibration
got a dedicated hardware block which is already supported. This property
here is used to align with mipi-calibration logic used by Tegra114+.

Signed-off-by: Svyatoslav Ryhel &lt;clamor95@gmail.com&gt;
Reviewed-by: Rob Herring (Arm) &lt;robh@kernel.org&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: display: tegra: document EPP, ISP, MPE and TSEC for Tegra114+</title>
<updated>2025-11-14T14:39:39Z</updated>
<author>
<name>Svyatoslav Ryhel</name>
</author>
<published>2025-10-16T07:41:49Z</published>
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<id>urn:sha1:a0c70244e5a877be917fc6aaf1e58a4debd99c4d</id>
<content type='text'>
The current EPP, ISP and MPE schemas are largely compatible with Tegra114+,
requiring only minor adjustments. Additionally, the TSEC schema for the
Security engine, which is available from Tegra114 onwards, is included.

Signed-off-by: Svyatoslav Ryhel &lt;clamor95@gmail.com&gt;
Reviewed-by: Rob Herring (Arm) &lt;robh@kernel.org&gt;
Reviewed-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: display: tegra: Move avdd-dsi-csi-supply from VI to CSI</title>
<updated>2025-09-11T16:02:54Z</updated>
<author>
<name>Svyatoslav Ryhel</name>
</author>
<published>2025-09-06T13:53:33Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=6b670e53ac6ecd531d90324e9ef87a029d2c98b9'/>
<id>urn:sha1:6b670e53ac6ecd531d90324e9ef87a029d2c98b9</id>
<content type='text'>
The avdd-dsi-csi-supply is CSI power supply, it has nothing to do with
VI, like same supply is used with DSI and has nothing to do with DC.
Move it to correct place.

Signed-off-by: Svyatoslav Ryhel &lt;clamor95@gmail.com&gt;
Acked-by: Rob Herring (Arm) &lt;robh@kernel.org&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: display: tegra: Document Tegra124 MIPI</title>
<updated>2025-03-07T16:08:17Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2025-03-06T17:48:02Z</published>
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<id>urn:sha1:5a3d45a111cb9154a59d1c7e35dece1ceab0b65c</id>
<content type='text'>
The Tegra124 MIPI hardware block is very similar to the one found on
earlier chip generations. Add a corresponding compatible string.

Acked-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: display: tegra: Allow dma-coherent on Tegra194 and later</title>
<updated>2024-04-26T15:40:18Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2023-04-20T12:12:33Z</published>
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<id>urn:sha1:22b92b28fcf4f7748279c4071c63e53fecfacc2d</id>
<content type='text'>
Tegra194 and later chips have a coherency fabric, so some devices can be
marked as DMA coherent to avoid unnecessary cache maintenance.

Reviewed-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: Fix typos</title>
<updated>2023-08-18T16:32:25Z</updated>
<author>
<name>Bjorn Helgaas</name>
</author>
<published>2023-08-14T21:28:21Z</published>
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<id>urn:sha1:47aab53331effedd3f5a6136854bd1da011f94b6</id>
<content type='text'>
Fix typos in Documentation/devicetree/bindings.  The changes are in
descriptions or comments where they shouldn't affect functionality.

Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Link: https://lore.kernel.org/r/20230814212822.193684-3-helgaas@kernel.org
Signed-off-by: Rob Herring &lt;robh@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: display: tegra: vi: add 'vip' property and example</title>
<updated>2023-05-25T11:04:47Z</updated>
<author>
<name>Luca Ceresoli</name>
</author>
<published>2023-04-18T08:00:36Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=f17aa778ac36298a8b5648984de6f1b8c8d87705'/>
<id>urn:sha1:f17aa778ac36298a8b5648984de6f1b8c8d87705</id>
<content type='text'>
The Tegra20 VI peripheral can receive parallel input from the VIP parallel
input module. Add it to the allowed properties and augment the existing
nvidia,tegra20-vi example to show a 'vip' property.

Signed-off-by: Luca Ceresoli &lt;luca.ceresoli@bootlin.com&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Hans Verkuil &lt;hverkuil-cisco@xs4all.nl&gt;
</content>
</entry>
<entry>
<title>dt-bindings: display: tegra: add Tegra20 VIP</title>
<updated>2023-05-25T11:04:47Z</updated>
<author>
<name>Luca Ceresoli</name>
</author>
<published>2023-04-18T08:00:35Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=7e3d507ab040c0f21f680c6e23d8432623867b3c'/>
<id>urn:sha1:7e3d507ab040c0f21f680c6e23d8432623867b3c</id>
<content type='text'>
VIP is the parallel video capture component within the video input
subsystem of Tegra20 (and other Tegra chips, apparently).

Signed-off-by: Luca Ceresoli &lt;luca.ceresoli@bootlin.com&gt;
Reviewed-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Reviewed-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Hans Verkuil &lt;hverkuil-cisco@xs4all.nl&gt;
</content>
</entry>
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