kernel.git/Documentation/devicetree/bindings/display/msm, branch master

dt-bindings: display/msm: qcom,sm8750-mdss: Fix model typo

2026-03-05T23:53:03Z

Fix obvious model typo (SM8650->SM8750) in the description. Signed-off-by: Krzysztof Kozlowski Fixes: 6b93840116df ("dt-bindings: display/msm: qcom,sm8750-mdss: Add SM8750") Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/707192/ Link: https://lore.kernel.org/r/20260225173419.125565-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov

dt-bindings: display: msm: Fix reg ranges and clocks on Glymur

2026-03-05T23:53:03Z

The Glymur platform has four DisplayPort controllers. The hardware supports four streams (MST) per controller. However, on Glymur the first three controllers only have two streams wired to the display subsystem, while the fourth controller operates in single-stream mode. Add a dedicated clause for the Glymur compatible to require the register ranges for all four stream blocks, while allowing either one pixel clock (for the single-stream controller) or two pixel clocks (for the remaining controllers). Update the Glymur MDSS schema example by adding the missing p2, p3, mst2link and mst3link register blocks. Without these, the bindings validation fails. Also replace the made-up register addresses with the actual addresses from the first controller to match the SoC devicetree description. Cc: stable@vger.kernel.org # v6.19 Fixes: 8f63bf908213 ("dt-bindings: display: msm: Document the Glymur DiplayPort controller") Fixes: 1aee577bbc60 ("dt-bindings: display: msm: Document the Glymur Mobile Display SubSystem") Signed-off-by: Abel Vesa Reviewed-by: Krzysztof Kozlowski Patchwork: https://patchwork.freedesktop.org/patch/708518/ Link: https://lore.kernel.org/r/20260303-glymur-fix-dp-bindings-reg-clocks-v4-1-1ebd9c7c2cee@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov

dt-bindings: display/msm: qcom, kaanapali-mdss: Add Kaanapali

2026-01-21T00:03:57Z

Kaanapali introduces DPU 13.0.0 and DSI 2.10. Compared to SM8750, Kaanapali has significant register changes, making it incompatible with SM8750. So add MDSS/MDP display subsystem for Qualcomm Kaanapali. Co-developed-by: Yongxing Mou Signed-off-by: Yongxing Mou Reviewed-by: Krzysztof Kozlowski Signed-off-by: Yuanjie Yang Patchwork: https://patchwork.freedesktop.org/patch/698700/ Link: https://lore.kernel.org/r/20260115092749.533-5-yuanjie.yang@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov

dt-bindings: display/msm: dsi-controller-main: Add Kaanapali

2026-01-21T00:03:57Z

The DSI registers on the Kaanapali platform differ from those on SM8750. So add DSI for Kaanapali to compatible these changes. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Yuanjie Yang Patchwork: https://patchwork.freedesktop.org/patch/698698/ Link: https://lore.kernel.org/r/20260115092749.533-4-yuanjie.yang@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov

dt-bindings: display/msm: dsi-phy-7nm: Add Kaanapali DSI PHY

2026-01-21T00:03:57Z

The DSI PHY registers on the Kaanapali platform differ from those on SM8750. So add DSI PHY for Kaanapali to compatible these changes. Acked-by: Krzysztof Kozlowski Signed-off-by: Yuanjie Yang Patchwork: https://patchwork.freedesktop.org/patch/698696/ Link: https://lore.kernel.org/r/20260115092749.533-3-yuanjie.yang@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov

dt-bindings: display/msm: qcom, kaanapali-dpu: Add Kaanapali

2026-01-21T00:03:57Z

Add DPU version 13.0 for Qualcomm Kaanapali Soc. The Kaanapali DPU and SM8750 have significant differences, including additions and removals of registers, as well as changes in register addresses. Acked-by: Rob Herring (Arm) Signed-off-by: Yuanjie Yang Patchwork: https://patchwork.freedesktop.org/patch/698694/ Link: https://lore.kernel.org/r/20260115092749.533-2-yuanjie.yang@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov

Merge tag 'v6.19-rc1' into msm-next

2026-01-20T22:06:55Z

Merge Linux 6.19-rc1 in order to catch up with other changes (e.g. UBWC config database defining UBWC_6). Signed-off-by: Dmitry Baryshkov

dt-bindings: display/msm/gpu: Straighten out reg-names on A619L/610/702

2026-01-18T15:15:56Z

These GPUs have physically have the same regions as the base case ("main" + "cx_mem" + "cx_dbgc"). Remove the specific override. Signed-off-by: Konrad Dybcio Acked-by: Rob Herring (Arm) Patchwork: https://patchwork.freedesktop.org/patch/696547/ Message-ID: <20251229-topic-6115_2290_gpu_dbgc-v1-1-4a24d196389c@oss.qualcomm.com> Signed-off-by: Rob Clark

dt-bindings: display/msm/rgmu: Document A612 RGMU

2026-01-15T22:12:33Z

RGMU a.k.a Reduced Graphics Management Unit is a small state machine with the sole purpose of providing IFPC (Inter Frame Power Collapse) support. Compared to GMU, it doesn't manage GPU clock, voltage scaling, bw voting or any other functionalities. All it does is detect an idle GPU and toggle the GDSC switch. As it doesn't access DDR space, it doesn't require iommu. So far, only Adreno 612 GPU has an RGMU core. Document it in qcom,adreno-rgmu.yaml. Signed-off-by: Jie Zhang Signed-off-by: Akhil P Oommen Reviewed-by: Krzysztof Kozlowski Patchwork: https://patchwork.freedesktop.org/patch/696679/ Message-ID: <20251231-qcs615-spin-2-v6-4-da87debf6883@oss.qualcomm.com> Signed-off-by: Rob Clark

dt-bindings: display/msm: gpu: Document A612 GPU

2026-01-15T22:12:33Z

A612 GPU has a new IP called RGMU (Reduced Graphics Management Unit) which replaces GMU. But it doesn't do clock or voltage scaling. So we need the gpu core clock in the GPU node along with the power domain to do clock and voltage scaling from the kernel. Update the bindings to describe this GPU. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Akhil P Oommen Patchwork: https://patchwork.freedesktop.org/patch/696676/ Message-ID: <20251231-qcs615-spin-2-v6-3-da87debf6883@oss.qualcomm.com> Signed-off-by: Rob Clark