kernel.git/Documentation/devicetree/bindings/clock/st, branch linux-4.6.y

drivers: clk: st: Correct the pll-type for A9 for stih418

2015-10-09T06:52:59Z

Add support for new PLL-type for stih418 A9-PLL. Currently the 407_A9_PLL type being used, it is corrected with this patch 4600c28 PLL allows to reach higher frequencies so its programming algorithm is extended. Signed-off-by: Pankaj Dev Signed-off-by: Gabriel Fernandez Signed-off-by: Stephen Boyd

ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x

2015-07-22T09:41:33Z

Use a generic name for this kind of PLL Signed-off-by: Gabriel Fernandez Signed-off-by: Maxime Coquelin

clk: st: Spelling s/stucture/structure/

2014-10-29T13:41:02Z

Signed-off-by: Geert Uytterhoeven Cc: Mike Turquette Signed-off-by: Jiri Kosina

clk: st: Adds Flexgen clock binding

2014-07-29T05:36:23Z

A Flexgen structure is composed by: - a clock cross bar (represented by a mux element) - a pre and final dividers (represented by a divider and gate elements) Signed-off-by: Gabriel Fernandez Acked-by: Peter Griffin Signed-off-by: Mike Turquette

clk: st: Update ST clock binding documentation

2014-07-29T05:35:17Z

Naming convention was changed in dts file but the clock binding documentation hasn't been updated. Signed-off-by: Gabriel Fernandez Acked-by: Peter Griffin Signed-off-by: Mike Turquette

clk: st: Adds quadfs clock binding

2014-03-25T22:59:31Z

Signed-off-by: Gabriel Fernandez Signed-off-by: Mike Turquette

clk: st: Adds clockgen-vcc and clockgen-mux clock binding

2014-03-25T22:59:31Z

Signed-off-by: Gabriel Fernandez Signed-off-by: Mike Turquette

clk: st: Adds clockgen clock binding

2014-03-25T22:59:30Z

Signed-off-by: Gabriel Fernandez Signed-off-by: Mike Turquette

clk: st: Adds divmux and prediv clock binding

2014-03-25T22:59:29Z

Signed-off-by: Gabriel Fernandez Signed-off-by: Mike Turquette