kernel.git/Documentation/devicetree/bindings/bus, branch linux-4.12.y

bus:qcom : Fix typo in qcom,ebi2.txt

2017-01-09T18:18:32Z

This patch fix 2 spelling typos found in qcom,ebi2.txt Signed-off-by: Masanari Iida Reviewed-by: Linus Walleij Signed-off-by: Rob Herring

Merge tag 'tegra-for-4.10-bus' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers

2016-11-19T02:32:57Z

bus: Add Tegra GMI support This provides a driver to enable the use of the Generic Memory Interface found on Tegra SoCs that can host various types of high-speed devices. * tag 'tegra-for-4.10-bus' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: bus: Add support for Tegra Generic Memory Interface dt/bindings: Add bindings for Tegra GMI controller Signed-off-by: Olof Johansson

dt/bindings: Add bindings for Tegra GMI controller

2016-11-15T16:27:52Z

Document the devicetree bindings for the Generic Memory Interface (GMI) bus driver found on Tegra SOCs. Signed-off-by: Mirza Krak Tested-by: Marcel Ziswiler Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board Acked-by: Rob Herring Signed-off-by: Thierry Reding

bus: davinci: add support for da8xx bus master priority control

2016-11-14T11:50:29Z

Create the driver for the da8xx master peripheral priority configuration and implement support for writing to the three Master Priority registers on da850 SoCs. Reviewed-by: Kevin Hilman Acked-by: Rob Herring Signed-off-by: Bartosz Golaszewski [nsekhar@ti.com: subject line adjustment] Signed-off-by: Sekhar Nori

bus: qcom: add EBI2 device tree bindings

2016-09-08T13:26:21Z

This adds device tree bindings for the External Bus Interface 2, EBI2 to the Qualcomm SoC drivers. Cc: devicetree@vger.kernel.org Acked-by: Rob Herring Signed-off-by: Linus Walleij

dt-bindings: bus: Add documentation for Tegra210 ACONNECT

2016-07-01T14:35:43Z

Add binding documentation for the Tegra ACONNECT bus that is part of the Audio Processing Engine (APE) on Tegra210. The ACONNECT bus is used to access devices within the APE subsystem. The APE is located in a separate power domain and so accesses made to the ACONNECT require the power domain to be enabled as well as some platform specific clocks. Signed-off-by: Jon Hunter Acked-by: Rob Herring Signed-off-by: Thierry Reding

memory: omap-gpmc: Move device tree binding to correct location

2016-04-15T08:54:03Z

omap-gpmc.c is a memory controller so move the binding to the right place. Signed-off-by: Roger Quadros Acked-by: Rob Herring Acked-by: Tony Lindgren

memory: omap-gpmc: Implement IRQ domain for NAND IRQs

2016-04-15T08:52:28Z

GPMC provides 2 interrupts for NAND use. i.e. fifoevent and termcount. Use IRQ domain for this. NAND device tree node can then get the necessary interrupts by using gpmc as the interrupt parent. Legacy boot uses gpmc_get_client_irq to get the NAND interrupts from the GPMC IRQ domain. Get rid of custom bitmasks and use IRQ domain for that as well. Signed-off-by: Roger Quadros Acked-by: Rob Herring Acked-by: Tony Lindgren

dt-bindings: bus: ti-gpmc: Add AAD timings properties

2016-02-08T14:22:03Z

In order to support advanced AAD timings, add these properties to the DT GPMC bindings. Signed-off-by: Neil Armstrong Acked-by: Tony Lindgren Acked-by: Rob Herring Signed-off-by: Roger Quadros

bus: uniphier-system-bus: add UniPhier System Bus driver

2015-12-22T19:22:39Z

The UniPhier System Bus is an external bus that connects on-board devices to the UniPhier SoC. Each bank (chip select) is dynamically mapped to the CPU-viewed address base via the bus controller. The bus controller must be configured before any access to the bus. This driver parses the "ranges" property of the System Bus node and initialized the bus controller. After the bus becomes ready, devices below it are populated. Note: Each bank can be mapped anywhere in the supported address space; there is nothing preventing us from assigning bank 0 on 0x42000000, 0x43000000, or anywhere as long as such region is not used by others. So, the "ranges" is just one possible software configuration, which does not seem to fit in device tree because device tree is a hardware description language. However, of_translate_address() requires "ranges" in every bus node between CPUs and device mapped on the CPU address space. In other words, "ranges" properties must be statically defined in device tree. After some discussion, I decided the dynamic address reassignment by the driver is too bothersome. Instead, the device tree should provide a reasonable translation setup that the OS can rely on. Signed-off-by: Masahiro Yamada Acked-by: Rob Herring Acked-by: Arnd Bergmann Signed-off-by: Olof Johansson