kernel.git/Documentation/devicetree/bindings/arm/altera, branch linux-4.1.y

arm: dts: Add Altera SDRAM EDAC bindings & devicetree entries.

2014-09-04T15:15:52Z

Add the Altera SDRAM EDAC bindings and device tree changes to the Altera SoC project. There was a discussion thread on whether this driver should be an mfd driver or just make use of syscon, which is already a mfd. Ultimately, the decision to use a simple syscon interface was reached.[1] [1] https://lkml.org/lkml/2014/7/30/514 Signed-off-by: Thor Thayer Acked-by: Pavel Machek [dinguyen] cleaned-up commit header and remove version history. Signed-off-by: Dinh Nguyen

Documentation: dt: reset: move socfpga-reset

2014-05-06T03:33:17Z

Instead of having the documentation for the socfpga-reset controller in a vendor specific directory, move it to the reset folder to all the other reset drivers. Signed-off-by: Steffen Trumtrar Signed-off-by: Dinh Nguyen

Documentation: dt: socfpga: add reset-cells property

2014-05-06T03:33:17Z

To be able to use the reset-controller framework, the property #reset-cells is mandatory. Signed-off-by: Steffen Trumtrar Signed-off-by: Dinh Nguyen

ARM: socfpga: Add clock entries into device tree

2013-04-15T03:17:59Z

Adds the main PLL clock groups for SOCFPGA into device tree file so that the clock framework to query the clock and clock rates appropriately. $cat /sys/kernel/debug/clk/clk_summary clock enable_cnt prepare_cnt rate --------------------------------------------------------------------- osc1 2 2 25000000 sdram_pll 0 0 400000000 s2f_usr2_clk 0 0 66666666 ddr_dq_clk 0 0 200000000 ddr_2x_dqs_clk 0 0 400000000 ddr_dqs_clk 0 0 200000000 periph_pll 2 2 500000000 s2f_usr1_clk 0 0 50000000 per_base_clk 4 4 100000000 per_nand_mmc_clk 0 0 25000000 per_qsi_clk 0 0 250000000 emac1_clk 1 1 125000000 emac0_clk 0 0 125000000 main_pll 1 1 1600000000 cfg_s2f_usr0_clk 0 0 100000000 main_nand_sdmmc_clk 0 0 100000000 main_qspi_clk 0 0 400000000 dbg_base_clk 0 0 400000000 mainclk 0 0 400000000 mpuclk 1 1 800000000 smp_twd 1 1 200000000 Signed-off-by: Dinh Nguyen Reviewed-by: Pavel Machek Signed-off-by: Olof Johansson

arm: socfpga: Add SMP support for actual socfpga harware

2013-02-12T03:37:26Z

Because the CPU1 start address is different for socfpga-vt and socfpga-cyclone5, we add code to use the correct CPU1 start addr. Signed-off-by: Dinh Nguyen Signed-off-by: Pavel Machek Cc: Russell King Cc: Arnd Bergmann Cc: Olof Johansson Cc: Rob Herring Cc: Grant Likely Signed-off-by: Olof Johansson

ARM: socfpga: Enable SMP for socfpga

2012-10-26T12:59:39Z

Enable SMP for the SOCFPGA platform. Signed-off-by: Pavel Machek Signed-off-by: Dinh Nguyen Reviewed-by: Rob Herring Signed-off-by: Arnd Bergmann